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Commit Graph

7 Commits

Author SHA1 Message Date
Fabien Dessenne
4b562de4e2
spi: stm32-qspi: manage the get_irq error case
During probe, check the "get_irq" error value.

Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-05-02 10:37:56 +09:00
Ludovic Barre
245308c621
spi: stm32-qspi: add dma support
This patch adds the dma support for the stm32-qspi hardware.
The memory buffer constraints (lowmem, vmalloc, kmap) are taken into
account by framework. In read mode, the memory map is preferred vs
dma (due to better throughput). If the dma transfer fails the buffer
is sent by polling.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-26 13:26:41 +00:00
Ludovic Barre
a88eceb17a
spi: stm32-qspi: add spi_master_put in release function
This patch adds spi_master_put in release function
to drop the controller's refcount.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-26 13:26:27 +00:00
kbuild test robot
43a8d240ee
spi: spi-mem: stm32-qspi: stm32_qspi_pm_ops can be static
Fixes: 2e541b64ee ("spi: spi-mem: stm32-qspi: add suspend/resume support")
Signed-off-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-20 17:20:14 +00:00
Ludovic Barre
2e541b64ee
spi: spi-mem: stm32-qspi: add suspend/resume support
This patch adds suspend and resume support for spi-stm32-qspi
drivers.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-15 17:14:32 +00:00
Ludovic Barre
5356c2c70e
spi: spi-mem: stm32-qspi: avoid memory corruption at low frequency
This patch solves a memory corruption seen at 8 MHz.
To avoid such issue, timeout counter is disabled.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-15 16:32:33 +00:00
Ludovic Barre
c530cd1d9d
spi: spi-mem: add stm32 qspi controller
The qspi controller is a specialized communication interface
targeting single, dual or quad SPI Flash memories (NOR/NAND).

It can operate in any of the following modes:
-indirect mode: all the operations are performed using the quadspi
 registers
-read memory-mapped mode: the external Flash memory is mapped to the
 microcontroller address space and is seen by the system as if it was
 an internal memory

tested on:
-NOR: mx66l51235l
-NAND: MT29F2G01ABAGD

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2018-10-19 13:32:56 +01:00