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Commit Graph

66 Commits

Author SHA1 Message Date
Maxime Bizon
0de663ef86 MIPS: BCM63xx: Add Broadcom 63xx CPU definitions.
Todo: Nothing ever detects CPU_BCM6338 but the code tests for it anyway.

Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-09-17 20:07:52 +02:00
Wu Fei
e0cc87f594 MIPS: Shrink the size of tlb handler
By combining swapper_pg_dir and module_pg_dir, several if conditions
can be eliminated from the tlb exception handler. The reason they
can be combined is that, the effective virtual address of vmalloc
returned is at the bottom, and of module_alloc returned is at the
top. It also fixes the bug in vmalloc(), which happens when its
return address is not covered by the first pgd.

Signed-off-by: Wu Fei <at.wufei@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-09-17 20:07:51 +02:00
Ralf Baechle
631330f584 MIPS: Build fix - include <linux/smp.h> into all smp_processor_id() users.
Some of the were relying into smp.h being dragged in by another header
which of course is fragile.  <asm/cpu-info.h> uses smp_processor_id()
only in macros and including smp.h there leads to an include loop, so
don't change cpu-info.h.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-24 18:34:39 +01:00
David Daney
fd062c847a MIPS: TLB support for hugetlbfs.
The TLB handlers need to check for huge pages and give them special
handling.  Huge pages consist of two contiguous sub-pages of physical
memory.

* Loading entrylo0 and entrylo1 need to be handled specially.

* The page mask must be set for huge pages and then restored after
  writing the TLB entries.

* The PTE for huge pages resides in the PMD, we halt traversal of the
  tables there.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:30 +01:00
David Daney
bd1437e49d MIPS: Remove unused parameters from iPTE_LW.
The l parameter to iPTE_LW() is unused. Remove it and from some of its
callers as well.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:30 +01:00
David Daney
faed5288af MIPS: Remove dead case label.
CPU_CAVIUM_OCTEON is mips_r2 which is handled before the switch.  This
label in the switch statement is dead code, so we remove it.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Reviewed by: David VomLehn <dvomlehn@cisco.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:26 +01:00
David Daney
41f0e4d041 MIPS: Allow R2 CPUs to turn off generation of 'ehb' instructions.
Some CPUs do not need ehb instructions after writing CP0 registers.
By allowing ehb generation to be overridden in
cpu-feature-overrides.h, we can save a few instructions in the TLB
handler hot paths.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:26 +01:00
David Daney
95affdda9b MIPS: Fold the TLB refill at the vmalloc path if possible.
Try to fold the 64-bit TLB refill handler opportunistically at the
beginning of the vmalloc path so as to avoid splitting execution flow in
half and wasting cycles for a branch required at that point then.  Resort
to doing the split if either of the newly created parts would not fit into
its designated slot.

Original-patch-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:26 +01:00
David Daney
e6f72d3aba MIPS: Replace some magic numbers with symbolic values in tlbex.c
The logic used to split the r4000 refill handler is liberally
sprinkled with magic numbers.  We attempt to explain what they are and
normalize them against a new symbolic value (MIPS64_REFILL_INSNS).

CC: David VomLehn <dvomlehn@cisco.com>
Reviewed-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-06-17 11:06:25 +01:00
Manuel Lauss
2f794d099d MIPS: Alchemy: MIPS hazard workarounds are not required.
The Alchemy manuals state:

"All pipeline hazards and dependencies are enforced by hardware interlocks
 so that any sequence of instructions is guaranteed to execute correctly.
 Therefore, it is not necessary to pad legacy MIPS hazards (such as
 load delay slots and coprocessor accesses) with NOPs."

Run-tested on Au12x0, without any ill effects.

Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-03-30 14:49:46 +02:00
Manuel Lauss
270717a8a0 MIPS: Alchemy: unify CPU model constants.
This patch removes the various CPU_AU1??? model constants in favor of
a single CPU_ALCHEMY one.

All currently existing Alchemy models are identical in terms of cpu
core and cache size/organization.  The parts of the mips kernel which
need to know the exact CPU revision extract it from the c0_prid register
already; and finally nothing else in-tree depends on those any more.

Should a new variant with slightly different "company options" and/or
"processor revision" bits in c0_prid appear, it will be supported
immediately (minus an exact model string in cpuinfo).

Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-03-30 14:49:45 +02:00
Shinya Kuribayashi
a644b2774d MIPS: NEC VR5500 processor support fixup
Current VR5500 processor support lacks of some functions which are
expected to be configured/synthesized on arch initialization.

Here're some VR5500A spec notes:

* All execution hazards are handled in hardware.

* Once VR5500A stops the operation of the pipeline by WAIT instruction,
  it could return from the standby mode only when either a reset, NMI
  request, or all enabled interrupts is/are detected.  In other words,
  if interrupts are disabled by Status.IE=0, it keeps in standby mode
  even when interrupts are internally asserted.

  Notes on WAIT: The operation of the processor is undefined if WAIT
  insn is in the branch delay slot.  The operation is also undefined
  if WAIT insn is executed when Status.EXL and Status.ERL are set to 1.

* VR5500A core only implements the Load prefetch.

With these changes, it boots fine.

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-03-11 21:11:07 +01:00
David Daney
ec454d8c4f MIPS: Add Cavium OCTEON slot into proper tlb category.
Expand the case statement for build_tlb_write_entry so that it does
the right thing on Cavium CPU variants.

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-01-11 09:57:24 +00:00
Thomas Bogendoerfer
e0cee3eea7 [MIPS] Fix WARNING: at kernel/smp.c:290
trap_init issues flush_icache_range(), which uses ipi functions to
get icache flushing done on all cpus. But this is done before interrupts
are enabled and caused WARN_ON messages. This changeset introduces
a new local_flush_icache_range() and uses it before interrupts (and
additional CPUs) are enabled to avoid this problem.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-09-05 21:24:11 +01:00
Thomas Bogendoerfer
326e2e1a59 [MIPS] R4700: Fix build_tlb_probe_entry
Treat R4700 like R4600 in build_tlb_probe_entry. Without this fix kernel
will lock up.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-06-05 18:13:14 +01:00
Thomas Bogendoerfer
b1ec4c8e48 [MIPS] Add missing 4KEC TLB refill handler
Early 4KEc were MIPS32r1 and therefore need some love to get a TLB
refill handler.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-04-01 15:46:33 +01:00
Ralf Baechle
234fcd1484 [MIPS] Fix loads of section missmatches
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-03-12 14:14:41 +00:00
Thiemo Seufer
e30ec4525d [MIPS] Split the micro-assembler from tlbex.c.
This patch moves the micro-assembler in a separate implementation, as
it is useful for further run-time optimizations. The only change in
behaviour is cutting down printk noise at kernel startup time.

Checkpatch complains about macro parameters which aren't protected by
parentheses. I believe this is a flaw in checkpatch, the paste operator
used in those macros won't work with parenthesised parameters.

Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-02-01 14:48:44 +00:00
Manuel Lauss
237cfee1db [MIPS] Alchemy: Au1210/Au1250 CPU support
This patch adds IDs for new Au1200 variants: Au1210 and Au1250.
They are essentially identical to the Au1200 except for the Au1210
which has a different SoC-ID in the PRId register [bits 31:24].
The Au1250 is a "Au1200 V0.2".

Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:59 +00:00
Franck Bui-Huu
92b1e6a64a [MIPS] tlbex.c: cleanup debug code
Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:57 +00:00
Franck Bui-Huu
cbdbe07f9d [MIPS] tlbex.c: use __cacheline_aligned instead of __tlb_handler_align
Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:57 +00:00
Franck Bui-Huu
f49b94d8c1 [MIPS] tlbex.c: cleanup include files
Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:56 +00:00
Franck Bui-Huu
a9af6041e9 [MIPS] tlbex.c: Cleanup __init usages.
Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:56 +00:00
Maciej W. Rozycki
619b6e18fc [MIPS] R4000/R4400 daddiu erratum workaround
This complements the generic R4000/R4400 errata workaround code and adds 
bits for the daddiu problem.  In most places it just modifies handwritten 
assembly code so that the assembler is allowed to use a temporary register 
as daddiu may now be treated as a macro that expands to a sequence of li 
and daddu.  It is the AT register or, where AT is unavailable or used 
explicitly for another purpose, an explicitly-named register is selected, 
using the .set at=<reg> feature added recently to gas.  This feature is 
only used if CONFIG_CPU_DADDI_WORKAROUNDS has been set, so if the 
workaround remains disabled, the required version of binutils stays 
unchanged.

 Similarly, daddiu instructions put in branch delay slots in noreorder 
fragments are now taken out of them and the assembler is allowed to 
reorder them itself as possible (which it does making the whole idea of 
scheduling them into delay slots manually questionable).

 Also in the very few places where such a simple conversion was not 
possible, a handcoded longer sequence is implemented.

 Other than that there are changes to code responsible for building the 
TLB fault and page clear/copy handlers to avoid daddiu as appropriate.  
These are only effective if the erratum is verified to be present at the 
run time.

 Finally there is a trivial update to __delay(), because it uses daddiu in 
a branch delay slot.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:55 +00:00
Ralf Baechle
161548bf35 [MIPS] tlbex: Cleanup handling of R2 hazards in TLB handlers.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-01-29 10:14:54 +00:00
Ralf Baechle
6f1ca1d286 [MIPS] Revert "[MIPS] tlbex.c: Cleanup __init usage."
This reverts commit aaf76a3245.

As requested by ranck Bui-Huu <fbuihuu@gmail.com>.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-13 00:53:00 +01:00
Franck Bui-Huu
aaf76a3245 [MIPS] tlbex.c: Cleanup __init usage.
Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:19 +01:00
Ralf Baechle
21a151d8ca [MIPS] checkfiles: Fix "need space after that ','" errors.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:15 +01:00
Ralf Baechle
10cc352907 [MIPS] Allow hardwiring of the CPU type to a single type for optimization.
This saves a few k on systems which only ever ship with a single CPU type.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:15 +01:00
Ralf Baechle
aeffdbbaff [MIPS] tlbex: Size optimize code by declaring a few functions inline.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:14 +01:00
Aurelien Jarno
1c0c13eb93 [MIPS] Add support for BCM47XX CPUs.
Note that the BCM4710 does not support the wait instruction, this
is not a mistake in the code.
    
It originally comes from the OpenWrt patches.
    
Cc: Michael Buesch <mb@bu3sch.de>
Cc: Felix Fietkau <nbd@openwrt.org>
Cc: Florian Schirmer <jolt@tuxbox.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-11 23:46:02 +01:00
Maciej W. Rozycki
8df5beac2a [MIPS] Workaround for 4Kc machine check exception
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-09-14 19:08:43 +01:00
Thiemo Seufer
603c338bdd [MIPS] TLB: Fix instruction bitmasks
Signed-Off-By: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-09-10 21:25:28 +01:00
Fuxin Zhang
2a21c7300b [MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2
Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-07-10 17:33:02 +01:00
David Rientjes
e8b6d40a00 [MIPS] tlbex: use __maybe_unused
Replace function instances of __attribute__((unused)) with
__maybe_unused.

Acked-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: David Rientjes <rientjes@google.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-05-11 14:28:33 +01:00
Atsushi Nemoto
656be92f9a [MIPS] Load modules to CKSEG0 if CONFIG_BUILD_ELF64=n
This is a patch to load 64-bit modules to CKSEG0 so that can be
compiled with -msym32 option.  This makes each module ~10% smaller.

* introduce MODULE_START and MODULE_END
* custom module_alloc()
* PGD for modules
* change XTLB refill handler synthesizer
* enable -msym32 for modules again
  (revert ca78b1a5c6a6e70e052d3ea253828e49b5d07c8a)

New XTLB refill handler looks like this:

80000080 dmfc0   k0,C0_BADVADDR
80000084 bltz    k0,800000e4			# goto l_module_alloc
80000088 lui     k1,0x8046			# %high(pgd_current)
8000008c ld      k1,24600(k1)			# %low(pgd_current)
80000090 dsrl    k0,k0,0x1b			# l_vmalloc_done:
80000094 andi    k0,k0,0x1ff8
80000098 daddu   k1,k1,k0
8000009c dmfc0   k0,C0_BADVADDR
800000a0 ld      k1,0(k1)
800000a4 dsrl    k0,k0,0x12
800000a8 andi    k0,k0,0xff8
800000ac daddu   k1,k1,k0
800000b0 dmfc0   k0,C0_XCONTEXT
800000b4 ld      k1,0(k1)
800000b8 andi    k0,k0,0xff0
800000bc daddu   k1,k1,k0
800000c0 ld      k0,0(k1)
800000c4 ld      k1,8(k1)
800000c8 dsrl    k0,k0,0x6
800000cc mtc0    k0,C0_ENTRYLO0
800000d0 dsrl    k1,k1,0x6
800000d4 mtc0    k1,C0_ENTRYL01
800000d8 nop
800000dc tlbwr
800000e0 eret
800000e4 dsll    k1,k0,0x2			# l_module_alloc:
800000e8 bgez    k1,80000008			# goto l_vmalloc
800000ec lui     k1,0xc000
800000f0 dsubu   k0,k0,k1
800000f4 lui     k1,0x8046			# %high(module_pg_dir)
800000f8 beq     zero,zero,80000000
800000fc nop
80000000 beq     zero,zero,80000090		# goto l_vmalloc_done
80000004 daddiu  k1,k1,0x4000
80000008 dsll32  k1,k1,0x0			# l_vmalloc:
8000000c dsubu   k0,k0,k1
80000010 beq     zero,zero,80000090		# goto l_vmalloc_done
80000014 lui     k1,0x8046			# %high(swapper_pg_dir)

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-11-30 01:14:44 +00:00
Ralf Baechle
242954b5aa [MIPS] 16K & 64K page size fixes
Derived from Peter Watkins <treestem@gmail.com>'s work.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-11-01 17:46:09 +00:00
Matt LaPlante
4b3f686d4a Attack of "the the"s in arch
The patch below corrects multiple occurances of "the the"
typos across several files, both in source comments and KConfig files.
There is no actual code changed, only text.  Note this only affects the /arch
directory, and I believe I could find many more elsewhere. :)

Signed-off-by: Adrian Bunk <bunk@stusta.de>
2006-10-03 22:21:02 +02:00
Thiemo Seufer
115f2a44e0 [MIPS] Print out TLB handler assembly for debugging.
Small update, using pr_debug and pr_info.

Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13 21:26:16 +01:00
Jörn Engel
6ab3d5624e Remove obsolete #include <linux/config.h>
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
2006-06-30 19:25:36 +02:00
Kumba
44d921b246 [MIPS] Treat R14000 like R10000.
Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-01 00:28:35 +01:00
Chris Dearman
c620953c32 [MIPS] Fix detection and handling of the 74K processor.
Nothing exciting; Linux just didn't know it yet so this is most adding
a value to a case statement.
    
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-01 00:28:30 +01:00
Ralf Baechle
41c594ab65 [MIPS] MT: Improved multithreading support.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-19 04:14:28 +02:00
Ralf Baechle
91b05e6776 [MIPS] Fix vectored interrupt support in TLB exception handler generator.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-19 04:14:13 +02:00
Ralf Baechle
8145095cd8 [MIPS] Remove CONFIG_BUILD_ELF64.
This option is no longer usable with supported compilers.  It will be
replaced by usage of -msym32 in a separate patch.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-21 13:27:46 +00:00
Ralf Baechle
1443e483e3 [MIPS] Scatter a bunch of __init over tlbex.c.
Found by make buildcheck.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-09 18:05:10 +00:00
Andrew Isaacson
93ce2f524e Add support for SB1A CPU.
Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:46 +01:00
Thiemo Seufer
f5b4d9563b R4600 v2.0 needs a nop before tlbp.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:17 +01:00
Ralf Baechle
7623debf26 Handle mtc0 - tlb write hazard for VR5432.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:12 +01:00
Ralf Baechle
1d40cfcd34 Avoid SMP cacheflushes. This is a minor optimization of startup but
will also avoid smp_call_function from doing stupid things when called
from a CPU that is not yet marked online.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:54 +01:00