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2 Commits

Author SHA1 Message Date
Geert Uytterhoeven
2570d4005d clk: renesas: r8a7796: Add watchdog core clocks
Add all core clocks related to the Watchdog Timer (WDT) controller on
the Renesas R-Car M3-W (r8a7796) SoC: OSC, Internal RCLK, and RCLK.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-09 09:53:47 +02:00
Geert Uytterhoeven
e4e2d7c388 clk: renesas: cpg-mssr: Add support for R-Car M3-W
Initial support for R-Car M3-W (r8a7796), including basic core clocks,
and SCIF2 (console) and INTC-AP (GIC) module clocks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
2016-06-06 11:58:35 +02:00