2
0
mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-19 18:53:52 +08:00
Commit Graph

7 Commits

Author SHA1 Message Date
Paul Mundt
9d56dd3b08 sh: Mass ctrl_in/outX to __raw_read/writeX conversion.
The old ctrl in/out routines are non-portable and unsuitable for
cross-platform use. While drivers/sh has already been sanitized, there
is still quite a lot of code that is not. This converts the arch/sh/ bits
over, which permits us to flag the routines as deprecated whilst still
building with -Werror for the architecture code, and to ensure that
future users are not added.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-01-26 12:58:40 +09:00
Paul Mundt
711e522d70 sh: Use local TLB flush for get_mmu_context() ASID exhaustion.
When get_mmu_context() runs out of new ASIDs it flushes the TLB and
wraps around. Despite the fact the ASIDs are tracked per-CPU, a global
TLB flush was being used. Switch this over to a local one, as matches
the intent.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-08-20 17:24:40 +09:00
Paul Mundt
7b2758228f sh: Conver to asm-generic/mmu_context.h.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-06-14 23:23:41 +09:00
Rusty Russell
74c86d6757 cpumask: use mm_cpumask() wrapper: sh
Makes code futureproof against the impending change to mm->cpu_vm_mask.

It's also a chance to use the new cpumask_ ops which take a pointer
(the older ones are deprecated, but there's no hurry for arch code).

Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-06-14 18:24:15 +09:00
Paul Mundt
8263a67e16 sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores.
This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores
that implement the PTAEX register and respective functionality. Presently
only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs).

The main change is in how the PTE is written out when loading the entry
in to the TLB, as well as in how the TLB entry is selectively flushed.

While SH-X2 extended mode splits out the memory-mapped U and I-TLB data
arrays for extra bits, extended ASID mode splits out the address arrays.
While we don't use the memory-mapped data array access, the address
array accesses are necessary for selective TLB flushes, so these are
implemented newly and replace the generic SH-4 implementation.

With this, TLB flushes in switch_mm() are almost non-existent on newer
parts.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2009-03-17 17:49:49 +09:00
Paul Mundt
35724a0aed sh: Fix up the cpu_asid() return value on nommu.
This ought to be unsigned long, rather than defaulting to int.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-12-22 18:44:03 +09:00
Paul Mundt
f15cbe6f1a sh: migrate to arch/sh/include/
This follows the sparc changes a439fe51a1.

Most of the moving about was done with Sam's directions at:

http://marc.info/?l=linux-sh&m=121724823706062&w=2

with subsequent hacking and fixups entirely my fault.

Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-07-29 08:09:44 +09:00