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Commit Graph

30 Commits

Author SHA1 Message Date
Shaik Ameer Basha
1d87db4d4e clk: samsung: exynos5420: correct sysmmu-mfc parent clocks
This patch corrects the wrong parent-child relationship
between sysmmu-mfc clocks.

Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:22 +02:00
Shaik Ameer Basha
6b5ae463e4 clk: samsung: exynos5420: update clocks for FSYS and FSYS2 blocks
This patch adds more clocks from FSYS and FSYS2 blocks
and uses GATE_IP_* registers for gating IPs.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:21 +02:00
Shaik Ameer Basha
6575fa76c3 clk: samsung: exynos5420: update clocks for WCORE block
This patch adds missing clocks for WCORE block.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:21 +02:00
Shaik Ameer Basha
0a22c30653 clk: samsung: exynos5420: update clocks for PERIS and GEN blocks
This patch fixes some parent-child relationships according
to the latest datasheet and adds more clocks related to
PERIS and GEN blocks.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:20 +02:00
Shaik Ameer Basha
faec151b50 clk: samsung: exynos5420: update clocks for PERIC block
This patch includes,
    1] renaming of the HSI2C clocks
    2] renaming of spi clocks according to the datasheet
    3] fixes for child-parent relationships
    4] adding of more clocks related to PERIC block
    5] use GATE_IP_* offsets instead of GATE_BUS_*

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:20 +02:00
Shaik Ameer Basha
424b673a05 clk: samsung: exynos5420: update clocks for DISP1 block
This patch corrects some child-parent clock relationships,
and updates the clocks according to the latest datasheet.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:19 +02:00
Shaik Ameer Basha
3fac5941da clk: samsung: exynos5420: update clocks for G2D and G3D blocks
This patch adds missing clocks of G2D block. It also removes
the aclkg3d alias from G3D block clocks.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:19 +02:00
Shaik Ameer Basha
4549d93d9c clk: samsung: exynos5420: fix parent clocks for mscl sysmmu
This patch fixes the parent clocks for mscl sysmmu.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:18 +02:00
Shaik Ameer Basha
02932381ca clk: samsung: exynos5420: update clocks for GSCL and MSCL blocks
This patch adds the missing GSCL and MSCL block clocks
and corrects some wrong parent-child relationships.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:18 +02:00
Shaik Ameer Basha
3a767b35c6 clk: samsung: exynos5420: add clocks for ISP block
This patch adds minimum set of clocks to gate ISP block for
power saving.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:17 +02:00
Shaik Ameer Basha
dbd713bb90 clk: samsung: exynos5420: Rename mux parent arrays
This patch renames the mux parent arrays as per the naming
convension followed by the other exynos specific clock drivers.
And it also renames "mout_cpu_kfc" clock to "mout_kfc".

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:17 +02:00
Arun Kumar K
2ce262f456 clk: samsung: exynos5420: Add clock IDs needed by GPU
Adds IDs for the clocks needed by the ARM Mali GPU
in exynos5420.

Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:40:16 +02:00
Sachin Kamat
53cb6342de clk: samsung: exynos5420: Fix VPLL lock offset
Set it as per the user manual.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:23:37 +02:00
Naveen Krishna Chatradhi
5b73721b60 clk: samsung: exynos5250/5420: Add gate clock for SSS module
This patch adds gating clock for SSS(Security SubSystem)
module on Exynos5250/5420.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
[t.figa: Fixed sort order and group name.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:23:26 +02:00
Rahul Sharma
976face4b4 clk/samsung: add support for multiple clock providers
Samsung CCF helper functions do not provide support to
register multiple Clock Providers for a given SoC. Due to
this limitation, SoC platforms are not able to use these
helpers for registering multiple clock providers and are
forced to bypass this layer.

This layer is modified accordingly to enable the support
for multiple clock providers.

Clock file for exynos4, exynos5250, exynos5420, exynos5440,
S3c64xx, S3c24xx are also modified as per changed helper functions.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
[t.figa: Modified s3c2410 clock driver as well]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-05-14 19:15:38 +02:00
Tomasz Figa
3efb251167 clk: samsung: Drop old suspend/resume code
Since all SoC drivers have been moved to local suspend/resume handling,
the old code can be safely dropped.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14 08:16:01 +09:00
Tomasz Figa
388c78851e clk: samsung: exynos5420: Move suspend/resume handling to SoC driver
Since there are multiple differences in how suspend/resume of particular
Exynos SoCs must be handled, SoC driver is better place for
suspend/resume handlers and so this patch moves them.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-02-14 08:16:00 +09:00
Andrzej Hajda
cba9d2fa8b clk: exynos5420: replace clock ID private enums with IDs from DT header
The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
2014-01-08 18:02:39 +01:00
Chander Kashyap
cdf64eeeb0 clk: exynos5420: fix cpll clock register offsets
Fixes cpll control and lock register offset values for Exynos5420 SoC.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-12-04 10:46:45 -08:00
Rahul Sharma
0044cbcd66 clk/exynos5420: assign dout_pixel id to pixel clock divider
dout_pixel is a new ID allocated for pixel clock divider. It is
queried in the driver to pass as the parent to hdmi clock while
switching between parents.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-29 17:48:12 -07:00
Rahul Sharma
4625f1b5d4 clk/exynos5420: add hdmi mux to change parents in hdmi driver
hdmi driver needs to change the parent of hdmi clock
to pixel clock or hdmiphy clock, based on the stability
of hdmiphy. This patch is exposing the mux for changing
the parent.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-29 17:48:06 -07:00
Rahul Sharma
14d87cda8d clk/exynos5420: fix the order of parents of hdmi mux
Listing sclk_hdmiphy at 0th position in the list of parents is
causing wrong configuration in reg SRC_DISP10.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-29 17:48:00 -07:00
Rahul Sharma
9b229d8b04 clk/exynos5420: add gate clock for mixer sysmmu
Adding sysmmu clock for mixer for exynos5420.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-29 17:47:45 -07:00
Rahul Sharma
c9f3f08159 clk/exynos5420: add sclk_hdmiphy to the list of special clocks
Add sclk_hdmiphy to the list of exposed clocks. This is required
by hdmi driver to change the parent of hdmi clock.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-29 17:46:57 -07:00
Sachin Kamat
202e5ae945 clk: exynos5420: Fix incorrect placement of __initdata
__initdata should be placed between the variable name and equal
sign for the variable to be placed in the intended section.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-08 15:57:36 -07:00
Sachin Kamat
a9381b3f9b clk: exynos5420: Make exynos5420_plls static
'exynos5420_plls' is used only in this file. Make is static.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-08 15:57:32 -07:00
Yadwinder Singh Brar
3ff6e0d8d6 clk: samsung: Add support to register rate_table for samsung plls
This patch defines a common rate_table which will contain recommended p, m, s,
k values for supported rates that needs to be changed for changing
corresponding PLL's rate.

Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-02 13:22:09 -07:00
Yadwinder Singh Brar
c898c6b7cb clk: samsung: Migrate exynos5420 to use common samsung_clk_register_pll()
This patch migrates exynos5420 pll registeration to use common
samsung_clk_register_pll() by intialising table of PLLs and adding PLLs to
unique id list of clocks.

Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-08-02 13:22:08 -07:00
Sachin Kamat
c7306229d3 clk: exynos5420: Staticize local symbols
Symbols referenced only in this file are made static.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2013-07-25 14:18:32 -07:00
Chander Kashyap
1609027fc2 clk: exynos5420: register clocks using common clock framework
The EXYNOS5420 clocks are statically listed and registered using
the Samsung specific common clock helper functions.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2013-06-19 04:09:34 +09:00