The PINMUX_GPIO macro takes a port name and a data mark, respectively of
the form GPIO_name and name_DATA. Modify the macro to take the name as a
single argument and derive the port name and data mark from it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Unlike all other PFC SoC data, the shx3 data prefix all static symbols
with shx3_. Remove the prefix to be consistent with the other source
files.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The SoC has a bank-style PFC. Replace the custom-defined macros with
common macros from sh-pfc.h.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Move the pin definition macros to a common header file.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Move macros defined in several SoC data files to a common location and
document them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
The gpio_get_data_reg() and gpio_setup_data_reg() functions both take an
argument named gpio. The argument contains a GPIO offset for the first
function and a pin index for the second one. Rename them to offset and
idx respectively to match the rest of the code.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
The typedef only conceals the real variable type without bringing any
additional value (see Documentation/CodingStyle, section 5.b). Moreover,
it polutes the pinmux namespace. Replace it with the integer type it
used to hide.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
The GPIO driver uses an array of sh_pfc_gpio_pin structures to store
per-GPIO pin data. The array size is miscomputed at allocation time by
using the number of the last pin instead of the number of pins. When the
pin space contains holes this leads to memory overallocation. Fix it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
The macro isn't used, remove it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Two integer field structures are needlesly defined as const. Remove the
const keyword.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
The SH_PFC_MARK_INVALID macro and the PINMUX_FLAG_TYPE, GPIO_CFG_REQ and
GPIO_CFG_FREE enum entries are used, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Most of the PORT_DATA_* macros are not used, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
The ranges are not used anymore, remove them.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
The PFC SHX3 SoC data contains a input_pu range used to configure
pull-up resistors using the legacy non-pinconf API. That API has been
removed from the driver, the range is thus not used anymore. Remove it.
If required, configuring pull-up resistors for the SHX3 can be
implemented using the pinconf API, as done for the SH-Mobile, R-Mobile
and R-Car platforms.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The PFC SH7786 SoC data contains a input_pu range used to configure
pull-up resistors using the legacy non-pinconf API. That API has been
removed from the driver, the range is thus not used anymore. Remove it.
If required, configuring pull-up resistors for the SH7786 can be
implemented using the pinconf API, as done for the SH-Mobile, R-Mobile
and R-Car platforms.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The PFC SH7785 SoC data contains a input_pu range used to configure
pull-up resistors using the legacy non-pinconf API. That API has been
removed from the driver, the range is thus not used anymore. Remove it.
If required, configuring pull-up resistors for the SH7785 can be
implemented using the pinconf API, as done for the SH-Mobile, R-Mobile
and R-Car platforms.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The PFC SH7757 SoC data contains a input_pu range used to configure
pull-up resistors using the legacy non-pinconf API. That API has been
removed from the driver, the range is thus not used anymore. Remove it.
If required, configuring pull-up resistors for the SH7757 can be
implemented using the pinconf API, as done for the SH-Mobile, R-Mobile
and R-Car platforms.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The PFC SH7724 SoC data contains a input_pu range used to configure
pull-up resistors using the legacy non-pinconf API. That API has been
removed from the driver, the range is thus not used anymore. Remove it.
If required, configuring pull-up resistors for the SH7724 can be
implemented using the pinconf API, as done for the SH-Mobile, R-Mobile
and R-Car platforms.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The PFC SH7723 SoC data contains a input_pu range used to configure
pull-up resistors using the legacy non-pinconf API. That API has been
removed from the driver, the range is thus not used anymore. Remove it.
If required, configuring pull-up resistors for the SH7723 can be
implemented using the pinconf API, as done for the SH-Mobile, R-Mobile
and R-Car platforms.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The PFC SH7722 SoC data contains input_pd and input_pu ranges used to
configure pull-down and pull-up resistors using the legacy non-pinconf
API. That API has been removed from the driver, the ranges are thus not
used anymore. Remove them.
If required, configuring pull-down and pull-up resistors for the SH7722
can be implemented using the pinconf API, as done for the SH-Mobile,
R-Mobile and R-Car platforms.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
The PFC SH7720 SoC data contains a input_pu range used to configure
pull-up resistors using the legacy non-pinconf API. That API has been
removed from the driver, the range is thus not used anymore. Remove it.
If required, configuring pull-up resistors for the SH7720 can be
implemented using the pinconf API, as done for the SH-Mobile, R-Mobile
and R-Car platforms.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
As devm_ioremap_resource() is used on probe, there is no need to explicitly
check the return value from platform_get_resource(), as this is something that
devm_ioremap_resource() takes care by itself.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There's no need to duplicate essentially the same functions. Let's
introduce static int pinctrl_pm_select_state() and make the other
related functions call that.
This allows us to add support later on for multiple active states,
and more optimized dynamic remuxing.
Note that we still need to export the various pinctrl_pm_select
functions as we want to keep struct pinctrl_state private to the
pinctrl code, and cannot replace those with inline functions.
Cc: Felipe Balbi <balbi@ti.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There are couple of sparse warnings we could avoid if we use a bit verbose
version of the code in byt_gpio_direction_output().
drivers/pinctrl/pinctrl-baytrail.c:266:45: warning: dubious: x | !y
drivers/pinctrl/pinctrl-baytrail.c:267:36: warning: dubious: x | !y
Additionally simplify a bit the code in byt_gpio_direction_input().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The introduced macro helps to convert struct gpio_chip to struct byt_gpio.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There is no need to have an additional variable in byt_gpio_reg().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There are two minor issues with indentation in the code. This patch fixes them.
No functional changes.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
this patch adds hibernation entries so that the sirf platform can
support suspend-to-disk.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- A large slew of improvements of the Genric pin configuration
support, and deployment in four different platforms:
Rockchip, Super-H PFC, ABx500 and TZ1090. Support BIAS_BUS_HOLD,
get device tree parsing and debugfs support into shape.
- We also have device tree support with generic naming conventions
for the generic pin configuration.
- Delete the unused and confusing direct pinconf API. Now state
transitions is *the* way to control pins and multiplexing.
- New drivers for Rockchip, TZ1090, and TZ1090 PDC.
- Two pin control states related to power management are now
handled in the device core: "sleep" and "idle", removing a lot
of boilerplate code in drivers. We do not yet know if this is
the final word for pin PM, but it already make things a lot
easier to handle.
- Handle sparse GPIO ranges passing a list of disparate pins, and
utilize these in the new BayTrail (x86 Atom SoC) driver.
- Make the sunxi (AllWinner) driver handle external interrupts.
- Make it possible for pinctrl-single to handle the case where
several pins are managed by a single register, and augment it to
handle sleep modes.
- Cleanups and improvements for the abx500 drivers.
- Move Sirf pin control drivers to their own directory, support
save/restore of context and add support for the SiRFatlas6 SoC.
- PMU muxing for the Dove pinctrl driver.
- Finalization and support for VF610 in the i.MX6 pinctrl driver.
- Smoothen out various Exynos rough edges.
- Generic cleanups of various kinds.
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Merge tag 'pinctrl-for-v3.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control changes from Linus Walleij:
- A large slew of improvements of the Genric pin configuration support,
and deployment in four different platforms: Rockchip, Super-H PFC,
ABx500 and TZ1090. Support BIAS_BUS_HOLD, get device tree parsing
and debugfs support into shape.
- We also have device tree support with generic naming conventions for
the generic pin configuration.
- Delete the unused and confusing direct pinconf API. Now state
transitions is *the* way to control pins and multiplexing.
- New drivers for Rockchip, TZ1090, and TZ1090 PDC.
- Two pin control states related to power management are now handled in
the device core: "sleep" and "idle", removing a lot of boilerplate
code in drivers. We do not yet know if this is the final word for
pin PM, but it already make things a lot easier to handle.
- Handle sparse GPIO ranges passing a list of disparate pins, and
utilize these in the new BayTrail (x86 Atom SoC) driver.
- Make the sunxi (AllWinner) driver handle external interrupts.
- Make it possible for pinctrl-single to handle the case where several
pins are managed by a single register, and augment it to handle sleep
modes.
- Cleanups and improvements for the abx500 drivers.
- Move Sirf pin control drivers to their own directory, support
save/restore of context and add support for the SiRFatlas6 SoC.
- PMU muxing for the Dove pinctrl driver.
- Finalization and support for VF610 in the i.MX6 pinctrl driver.
- Smoothen out various Exynos rough edges.
- Generic cleanups of various kinds.
* tag 'pinctrl-for-v3.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (82 commits)
pinctrl: vt8500: wmt: remove redundant dev_err call in wmt_pinctrl_probe()
pinctrl: remove bindings for pinconf options needing more thought
pinctrl: remove slew-rate parameter from tz1090
pinctrl: set unit for debounce time pinconfig to usec
pinctrl: more clarifications for generic pull configs
pinctrl: rip out the direct pinconf API
pinctrl-tz1090-pdc: add TZ1090 PDC pinctrl driver
pinctrl-tz1090: add TZ1090 pinctrl driver
pinctrl: samsung: Staticize drvdata_list
pinctrl: rockchip: Add missing irq_gc_unlock() call before return error
pinctrl: abx500: rework error path
pinctrl: abx500: suppress hardcoded value
pinctrl: abx500: factorize code
pinctrl: abx500: fix abx500_gpio_get()
pinctrl: abx500: fix abx500_pin_config_set()
pinctrl: abx500: Add device tree support
sh-pfc: Guard DT parsing with #ifdef CONFIG_OF
pinctrl: add Intel BayTrail GPIO/pinctrl support
pinctrl: fix pinconf_ops::pin_config_dbg_parse_modify kerneldoc
pinctrl: Staticize local symbols
...
Conflicts:
drivers/net/ethernet/ti/davinci_mdio.c
drivers/pinctrl/Makefile
A small but useful set of regmap updates this time around:
- An abstraction for bitfields within a register map contributed by
Srinivas Kandagatla, allowing drivers to cope more easily when
hardware designers randomly move things about (mainly when talking
to things like system controllers).
- Changes from Lars-Peter Clausen to allow the MMIO regmap to be used from
hard IRQ context.
- Small improvements to the cache infrastructure and performance,
including a default cache sync operation so now all regmaps can sync
easily.
There's also a pinctrl driver making use of the new bitfield API, merged
here for dependency reasons. There will be a simple add/add conflict
with the pinctrl tree as a result.
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Merge tag 'regmap-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap
Pull regmap updates from Mark Brown:
"A small but useful set of regmap updates this time around:
- An abstraction for bitfields within a register map contributed by
Srinivas Kandagatla, allowing drivers to cope more easily when
hardware designers randomly move things about (mainly when talking
to things like system controllers).
- Changes from Lars-Peter Clausen to allow the MMIO regmap to be used
from hard IRQ context.
- Small improvements to the cache infrastructure and performance,
including a default cache sync operation so now all regmaps can
sync easily.
There's also a pinctrl driver making use of the new bitfield API,
merged here for dependency reasons. There will be a simple add/add
conflict with the pinctrl tree as a result."
* tag 'regmap-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap:
pinctrl: st: Remove unnecessary use of of_match_ptr macro
pinctrl: st: fix return value check
pinctrl: st: Add pinctrl and pinconf support.
regmap: debugfs: Suppress cache for partial register files
regmap: Add regmap_field APIs
regmap: core: Cache all registers by default when cache is enabled
regmap: Implemented default cache sync operation
regmap: Make regmap-mmio usable from atomic contexts
regmap: regcache: Fixup locking for custom lock callbacks
regmap: debugfs: Fix return from regmap_debugfs_get_dump_start
regmap: debugfs: Don't mark lockdep as broken due to debugfs write
regmap: rbtree: Use range information to allocate nodes
regmap: rbtree: Factor out node allocation
regmap: Make regmap_check_range_table() a public API
regmap: Add support for discarding parts of the register cache
These are changes that arrived a little late before the merge
window or that have multiple dependencies on previous branches
so they did not fit into one of the earlier ones. There
are 10 branches merged here, a total of 39 non-merge commits.
Contents are a mixed bag for the above reasons:
* Two new SoC platforms: ST microelectronics stixxxx and
the TI 'Nspire' graphing calculator. These should have
been in the 'soc' branch but were a little late
* Support for the Exynos 5420 variant in mach-exynos,
which is based on the other exynos branches to avoid
conflicts.
* Various small changes for sh-mobile, ux500 and davinci
* Common clk support for MSM
Conflicts:
* In Kconfig.debug, various additions trivially conflict,
the list should be kept in alphabetical order when
resolving.
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Merge tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late changes from Arnd Bergmann:
"These are changes that arrived a little late before the merge window
or that have multiple dependencies on previous branches so they did
not fit into one of the earlier ones. There are 10 branches merged
here, a total of 39 non-merge commits. Contents are a mixed bag for
the above reasons:
* Two new SoC platforms: ST microelectronics stixxxx and the TI
'Nspire' graphing calculator. These should have been in the 'soc'
branch but were a little late
* Support for the Exynos 5420 variant in mach-exynos, which is based
on the other exynos branches to avoid conflicts.
* Various small changes for sh-mobile, ux500 and davinci
* Common clk support for MSM"
* tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (39 commits)
ARM: ux500: bail out on alien cpus
ARM: davinci: da850: adopt to pinctrl-single change for configuring multiple pins
serial: sh-sci: Initialise variables before access in sci_set_termios()
ARM: stih41x: Add B2020 board support
ARM: stih41x: Add B2000 board support
ARM: sti: Add DEBUG_LL console support
ARM: sti: Add STiH416 SOC support
ARM: sti: Add STiH415 SOC support
ARM: msm: Migrate to common clock framework
ARM: msm: Make proc_comm clock control into a platform driver
ARM: msm: Prepare clk_get() users in mach-msm for clock-pcom driver
ARM: msm: Remove clock-7x30.h include file
ARM: msm: Remove custom clk_set_{max,min}_rate() API
ARM: msm: Remove custom clk_set_flags() API
msm: iommu: Use clk_set_rate() instead of clk_set_min_rate()
msm: iommu: Convert to clk_prepare/unprepare
msm_sdcc: Convert to clk_prepare/unprepare
usb: otg: msm: Convert to clk_prepare/unprepare
msm_serial: Use devm_clk_get() and properly return errors
msm_serial: Convert to clk_prepare/unprepare
...
These changes are all driver specific and cross over between arm-soc
contents and some other subsystem, in these cases cpufreq, crypto,
dma, pinctrl, mailbox and usb, and the subsystem owners agreed to
have these changes merged through arm-soc. As we proceed to untangle
the dependencies between platform code and driver code, the amount of
changes in this category is fortunately shrinking, for 3.11 we have
16 branches here and 101 non-merge changesets, the majority of which
are for the stedma40 dma engine driver used in the ux500 platform.
Cleaning up that code touches multiple subsystems, but gets rid
of the dependency in the end.
The mailbox code moved out from mach-omap2 to drivers/mailbox
is an intermediate step and is still omap specific at the moment.
Patches exist to generalize the subsystem and add other drivers
with the same API, but those did not make it for 3.11.
Conflicts:
* In cpu-db8500.c results from the removal of the u8500_of_init_devices
function in combination with the split of u8500_auxdata_lookup.
* In arch/arm/mach-omap2/devices.c, the includes got reshuffled.
we need to keep linux/wl12xx.h and linux/platform_data/mailbox-omap.h.
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Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver specific changes from Arnd Bergmann:
"These changes are all driver specific and cross over between arm-soc
contents and some other subsystem, in these cases cpufreq, crypto,
dma, pinctrl, mailbox and usb, and the subsystem owners agreed to have
these changes merged through arm-soc.
As we proceed to untangle the dependencies between platform code and
driver code, the amount of changes in this category is fortunately
shrinking, for 3.11 we have 16 branches here and 101 non-merge
changesets, the majority of which are for the stedma40 dma engine
driver used in the ux500 platform. Cleaning up that code touches
multiple subsystems, but gets rid of the dependency in the end.
The mailbox code moved out from mach-omap2 to drivers/mailbox is an
intermediate step and is still omap specific at the moment. Patches
exist to generalize the subsystem and add other drivers with the same
API, but those did not make it for 3.11."
* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (101 commits)
crypto: ux500: use dmaengine_submit API
crypto: ux500: use dmaengine_prep_slave_sg API
crypto: ux500: use dmaengine_device_control API
crypto: ux500/crypt: add missing __iomem qualifiers
crypto: ux500/hash: add missing static qualifiers
crypto: ux500/hash: use readl on iomem addresses
dmaengine: ste_dma40: Declare memcpy config as static
ARM: ux500: Remove mop500_snowball_ethernet_clock_enable()
ARM: ux500: Correct the EN_3v3 regulator's on/off GPIO
ARM: ux500: Provide a AB8500 GPIO Device Tree node
gpio: rcar: fix gpio_rcar_of_table
gpio-rcar: Remove #ifdef CONFIG_OF around OF-specific sections
gpio-rcar: Reference core gpio documentation in the DT bindings
clk: exynos5250: Add enum entries for divider clock of i2s1 and i2s2
ARM: dts: Update Samsung I2S documentation
ARM: dts: add clock provider information for i2s controllers in Exynos5250
ARM: dts: add Exynos audio subsystem clock controller node
clk: samsung: register audio subsystem clocks using common clock framework
ARM: dts: use #include for all device trees for Samsung
pinctrl: s3c24xx: use correct header for chained_irq functions
...
These changes from 30 individual branches for the most part update device
tree files, but there are also a few source code changes that have crept
in this time, usually in order to atomically move over a driver from
using hardcoded data to DT probing.
A number of platforms change their DT files to use the C preprocessor,
which is causing a bit of churn, but that is hopefully only this once.
There are a few conflicts with the other branches unfortunately:
* in exynos5440.dtsi and kirkwood-6281.dtsi, device nodes are added
from multiple branches. Need to be careful to have the right
set of closing braces as git gets this one wrong.
* In kirkwood.dtsi, one 'ranges' line got split into two lines, while
another line got added. Order of the lines does not matter.
* in sama5d3.dtsi, some cleanup was merged the wrong way, causing
a bogus conflict. We want the 'dmas' and 'dma-names' properties
to get added here.
* Two lines got removed independently in arch/arm/mach-mxs/mach-mxs.c
* Contents get added independently in arch/arm/mach-omap2/cclock33xx_data.c
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Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device tree changes from Arnd Bergmann:
"These changes from 30 individual branches for the most part update
device tree files, but there are also a few source code changes that
have crept in this time, usually in order to atomically move over a
driver from using hardcoded data to DT probing.
A number of platforms change their DT files to use the C preprocessor,
which is causing a bit of churn, but that is hopefully only this once"
* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (372 commits)
ARM: at91: dt: rm9200ek: add spi support
ARM: at91: dt: rm9200: add spi support
ARM: at91/DT: at91sam9n12: add SPI DMA client infos
ARM: at91/DT: sama5d3: add SPI DMA client infos
ARM: at91/DT: fix SPI compatibility string
ARM: Kirkwood: Fix the internal register ranges translation
ARM: dts: bcm281xx: change comment to C89 style
ARM: mmc: bcm281xx SDHCI driver (dt mods)
ARM: nomadik: add the new clocks to the device tree
clk: nomadik: implement the Nomadik clocks properly
ARM: dts: omap5-uevm: Provide USB Host PHY clock frequency
ARM: dts: omap4-panda: Fix DVI EDID reads
ARM: dts: omap4-panda: Add USB Host support
arm: mvebu: enable mini-PCIe connectors on Armada 370 RD
ARM: shmobile: irqpin: add a DT property to enable masking on parent
ARM: dts: AM43x EPOS EVM support
ARM: dts: OMAP5: Add bandgap DT entry
ARM: dts: AM33XX: Add pinmux configuration for CPSW to am335x EVM
ARM: dts: AM33XX: Add pinmux configuration for CPSW to EVMsk
ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
...
This is a DT only driver and st_pctl_of_match is always compiled
in. Hence of_match_ptr is unnecessary.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
In case of error, the function pinctrl_register() returns
NULL not ERR_PTR(). The IS_ERR() test in the return value
check should be replaced with NULL test.
The function syscon_regmap_lookup_by_phandle() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check
should be replaced with IS_ERR().
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
There is a error message within devm_ioremap_resource
already, so remove the dev_err call to avoid redundant
error message.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Acked-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- add pinctrl support for exynos5420
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Merge tag 'soc-exynos5420-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/late
From Kukjin Kim, this adds pinctrl support for Exynos 5420.
* tag 'soc-exynos5420-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
pinctrl: exynos: add exynos5420 SoC specific data
ARM: dts: add pinctrl support to EXYNOS5420
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch add pinctrl support to ST SoCs.
About hardware:
ST Set-Top-Box parts have two blocks called PIO and PIO-mux which handle
pin configurations.
Each multi-function pin is controlled, driven and routed through the PIO
multiplexing block. Each pin supports GPIO functionality (ALT0) and
multiple alternate functions(ALT1 - ALTx) that directly connect the pin
to different hardware blocks. When a pin is in GPIO mode, Output Enable
(OE), Open Drain(OD), and Pull Up (PU) are driven by the related PIO
block. Otherwise the PIO multiplexing block configures these parameters
and retiming the signal.
About driver:
This pinctrl driver manages both PIO and PIO-mux block using pinctrl,
pinconf, pinmux, gpio subsystems. All the pinctrl related config
information can only come from device trees.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
Some options currently take arguments in unspecified driver-specific units.
As pointed out by Stephen Warren, driver specific values should not be part
of generic devicetree bindings describing the hardware.
Therefore remove the critical bindings again, before they become part of
an official release.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
As the binding for slew-rate is under discussion and seems to need
more tought it will get removed for now, so it doesn't get an offical
release.
Therefore remove it again from the only current user, tz1090.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Currently the debounce time pinconfig option uses an unspecified
"time units" unit. As pinconfig options should use SI units and a
real unit is also necessary for generic dt bindings, change it
to usec. Currently no driver is using the generic pinconfig option
for this, so the unit change is safe to do.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
From the inception ot the pin config API there has been the
possibility to get a handle at a pin directly and configure
its electrical characteristics. For this reason we had:
int pin_config_get(const char *dev_name, const char *name,
unsigned long *config);
int pin_config_set(const char *dev_name, const char *name,
unsigned long config);
int pin_config_group_get(const char *dev_name,
const char *pin_group,
unsigned long *config);
int pin_config_group_set(const char *dev_name,
const char *pin_group,
unsigned long config);
After the introduction of the pin control states that will
control pins associated with devices, and its subsequent
introduction to the device core, as well as the
introduction of pin control hogs that can set up states on
boot and optionally also at sleep, this direct pin control
API is a thing of the past.
As could be expected, it has zero in-kernel users.
Let's delete this API and make our world simpler.
Reported-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add a pin control driver for the TZ1090's low power pins via the
powerdown controller SOC_GPIO_CONTROL registers.
These pins have individually controlled pull-up, and group controlled
schmitt, slew-rate, drive-strength, and power-on-start (pos).
The pdc_gpio0 and pdc_gpio1 pins can also be muxed onto the
ir_mod_stable_out and ir_mod_power_out functions respectively. If no
function is set they remain in GPIO mode. These muxes can be overridden
by requesting them as GPIOs.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-doc@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add a pin control driver for the main pins on the TZ1090 SoC. This
doesn't include the low-power pins as they're controlled separately via
the Powerdown Controller (PDC) registers.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Rob Landley <rob@landley.net>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-doc@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
'drvdata_list' is used only in this file. Make it static.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
At several places, return value was not tested
and error output was missing.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- allow to get output GPIO value
- as there is no GPIO0 on ABX500, use correct offset with
abx500_gpio_get_bit()
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Update abx500_pin_config_set() in order to take in
account PIN_CONFIG_BIAS_DISABLE state to disable
pull up or pull down.
- Rework error path.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We use the same way to define pin muxing and pin configuration
than for nomadik. So pickup code from pinctrl_nomadik.c to be
able to implement pin multiplexing and pin configuration using
the device tree. Pin configuration uses generic parsing code.
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix a compilation error caused by pinconf_generic_parse_dt_config() not
being defined on !CONFIG_OF platforms by guarding the whole DT node
parsing code with #ifdef CONFIG_OF.
Defining a pinconf_generic_parse_dt_config() on !CONFIG_OF would have
been possible as well, but would have resulted in a larger code size on
!CONFIG_OF platforms (such as arch/sh).
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
tidyup MMC_D1 pin for r8a7778 SoC
fix two pin numbers and add HSCIF pin groups to r8a7790 SoC
add pinmux data for MMCIF and SDHI interfaces for r8a73a4 SoC
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Merge tag 'renesas-pinmux2-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers
From Simon Horman:
Second Round of Renesas ARM based SoC pinmux and GPIO update for v3.11
tidyup MMC_D1 pin for r8a7778 SoC
fix two pin numbers and add HSCIF pin groups to r8a7790 SoC
add pinmux data for MMCIF and SDHI interfaces for r8a73a4 SoC
* tag 'renesas-pinmux2-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
sh-pfc: r8a7778: tidyup MMC_D1 pin
pinctrl: r8a7790: fix two pin numbers
sh-pfc: r8a7790: add HSCIF pin groups
pinctrl: r8a73a4: add pinmux data for MMCIF and SDHI interfaces
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
__initdata annotations for the r8a7790 SoC by Morimoto-san.
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Merge tag 'renesas-cleanup-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/late
From Simon Horman:
Renesas ARM based SoC cleanups for v3.11
__initdata annotations for the r8a7790 SoC by Morimoto-san.
* tag 'renesas-cleanup-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (158 commits)
ARM: shmobile: r8a7790: add __initdata on resource and device data
Based on 'renesas-pinmux-for-v3.11' and 'renesas-soc-for-v3.11
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- use correct header for chained_irq functions for s3c24xx-pinctrl
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Merge tag 's3c24xx-pinctrl-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim:
based on s3c24xx-pinctrl
- use correct header for chained_irq functions for s3c24xx-pinctrl
* tag 's3c24xx-pinctrl-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
pinctrl: s3c24xx: use correct header for chained_irq functions
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- enable XHCI on exynos5
- enable Pinctrl on exynos4 and exynos5
- calling scu_enable() is only available on Cortex-A9
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Merge tag 'exynos-arch-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
From Kukjin Kim:
arch/arm/mach-exynos update
- enable XHCI on exynos5
- enable Pinctrl on exynos4 and exynos5
- calling scu_enable() is only available on Cortex-A9
* tag 'exynos-arch-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: call scu_enable() only in case of cortex-A9 processor
ARM: EXYNOS: Select PINCTRL_EXYNOS for exynos4/5 at chip level
ARM: EXYNOS: Enable XHCI support on exynos5
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Lee Jones' pinctrl compat ontology patches
- A real clock driver for the Nomadik, 100% DT-based
- Device tree changes for the Nomadik clocks
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Merge tag 'nomadik-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into next/dt
From Linus Walleij:
Nomadik DT and clock work:
- Lee Jones' pinctrl compat ontology patches
- A real clock driver for the Nomadik, 100% DT-based
- Device tree changes for the Nomadik clocks
* tag 'nomadik-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: nomadik: add the new clocks to the device tree
clk: nomadik: implement the Nomadik clocks properly
pinctrl/nomadik: Standardise Pinctrl compat string for Nomadik based platforms
ARM: nomadik: Standardise Nomadik STN8815 based Pinctrl compat string in the DTS
Conflicts:
arch/arm/boot/dts/ste-nomadik-s8815.dts
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
- Add devicetree support to timer, pinctrl (probe), I2C block,
watchdog, DMA controller and clocks.
- Piecewise add a device tree containing all peripherals.
- Delete the ATAG boot path.
- Delete redundant platform data and board files.
- Convert to multiplatform.
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Merge tag 'u300-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/soc
From Linus Walleij:
Device Tree and Multiplatform support for U300:
- Add devicetree support to timer, pinctrl (probe), I2C block,
watchdog, DMA controller and clocks.
- Piecewise add a device tree containing all peripherals.
- Delete the ATAG boot path.
- Delete redundant platform data and board files.
- Convert to multiplatform.
* tag 'u300-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: (40 commits)
ARM: u300: switch to using syscon regmap for board
ARM: u300: Update MMC configs for u300 defconfig
spi: pl022: use DMA by default when probing from DT
pinctrl: get rid of all platform data for coh901
ARM: u300: convert MMC/SD clock to device tree
ARM: u300: move the gated system controller clocks to DT
i2c: stu300: do not request a specific clock name
clk: move the U300 fixed and fixed-factor to DT
ARM: u300: remove register definition file
ARM: u300: add syscon node
ARM: u300 use module_spi_driver to register driver
ARM: u300: delete remnant machine headers
ARM: u300: convert to multiplatform
ARM: u300: localize <mach/u300-regs.h>
ARM: u300: delete <mach/irqs.h>
ARM: u300: delete <mach/hardware.h>
ARM: u300: push down syscon registers
ARM: u300: remove deps from debug macro
ARM: u300: move debugmacro to debug includes
ARM: u300: delete all static board data
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add Samsung EXYNOS5420 SoC specific data to enable pinctrl
support for all platforms based on EXYNOS5420.
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by : Sunil Joshi <joshi@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Previously if you had MACH_EXYNOS5_DT but not MACH_EXYNOS4_DT you'd be
missing the pincontrol definitions. Move PINCTRL selects to the arch
level since we should be enabling the code for all exynos variants.
Update the PINCTRL descriptions to indicate that PINCTRL_EXYNOS is not
for exynos5440. Also add basic dependencies for the PINCTRL_EXYNOS
kernel config.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
chained_irq_enter and chained_irq_exit moved to a real header
under linux/pinctrl instead of asm/.
Update the pinctrl driver to use the correct header and fix the
build error.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>`
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add support for gpio on Intel BayTrail platforms. BayTrail supports 3 banks
of gpios called SCORE, NCORE ans SUS with 102, 28 and 44 gpio pins.
Supports gpio interrupts and ACPI gpio events
Pins may be muxed to alternate function instead of gpio by firmware.
This driver does not touch the pin muxing and expect firmare
to set pin muxing and pullup/down properties properly.
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Symbols referenced only in this file are made static.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
'spear310_o2p' is referenced only in this file.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Some symbols referenced only in this file are made static.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
'bcm2835_gpio_pins' is used only in this file.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Support device instantiation through the device tree. The compatible
property is used to select the SoC pinmux information.
Set the gpio_chip device field to the PFC device to enable automatic
GPIO OF support.
Cc: devicetree-discuss@lists.ozlabs.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add the missing unlock before return from function pinctrl_find_gpio_range_from_pin()
in the error handling case.
Introduced by commit 2ff3477efd7086544b9e298fc63afab0645921b4.
(pinctrl: add pin list based GPIO ranges)
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
A level-triggered interrupt should be acked after the interrupt line
becomes inactive and before it is unmasked, or else another interrupt
will be immediately triggered. Acking before or after calling the
handler is not enough.
Signed-off-by: Luigi Semenzato <semenzato@chromium.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The three functions pinctrl_pm_select_default_state,
pinctrl_pm_select_sleep_state, and pinctrl_pm_select_idle_state
are used in drivers that can be loadable modules, and should
be exported.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Change the rockchip pinctrl driver to handle the arguments to the pull
pinconfig options correctly. So only accept non-0 values for the
pull options as the rockchip pin-controller can only turn pulls on and
off (this via BIAS_DISABLE).
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Make pinctrl-single able to handle suspend/resume events and change
hogged pins states accordingly.
Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
It will allow us to have a cleaner separation between the data needed by
the driver to work, and the core logic of the driver in itself, and will
allow having too much noise in the core driver in the future.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Allocating the temorary array in pinconf_generic_parse_dt_config on stack
might cause problems later on, when the number of options grows over time.
Therefore also allocate this array dynamically to be on the safe side.
Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds a shortcut when no valid pinconf properties are found
in the parsed dt node, to set the values immediately and return.
Suggested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The bias-pull-* options use values > 0 to indicate that the pull should
be activated and optionally also indicate the strength of the pull.
Therefore use an default value of 1 for these options.
Split the low-power-mode option into low-power-enable and -disable.
Update the documentation to describe the param arguments better.
Reported-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Traditionally, GPIO ranges are based on consecutive ranges of both GPIO
and pin numbers. This patch allows for GPIO ranges with arbitrary lists
of pin numbers.
Signed-off-by: Christian Ruppert <christian.ruppert@abilis.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This deletes the dependency on any platform data for
the COH901 pin controller. There is only one user in the
kernel, and if we at some point want to support more
variants, they shall provide their variant info through
the device tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch does nothing but reorder the functions to improve the
readability of a future patch.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The patch:
1984695 pinctrl: samsung: Protect bank registers with a spinlock
...added spinlocks to protect many accesses. However, the irq_mask
and irq_unmask functions still do an unprotected read/modify/write.
Add the spinlock there.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl-abx500.c: In function 'abx500_gpio_dbg_show_one':
pinctrl-abx500.c:534:14: warning: 'pud' may be used
uninitialized in this function [-Wuninitialized]
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This driver adds support the Cortex-A9 based SoCs from Rockchip,
so at least the RK2928, RK3066 (a and b) and RK3188.
Earlier Rockchip SoCs seem to use similar mechanics for gpio
handling so should be supportable with relative small changes.
Pull handling on the rk3188 is currently a stub, due to it being
a bit different to the earlier SoCs.
Pinmuxing as well as gpio (and interrupt-) handling tested on
a rk3066a based machine.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinconf_generic_parse_dt_config() takes a node as input and generates an
array of generic pinconfig values from the properties of this node.
As I couldn't find a mechanism to count the number of properties of a node
the function uses internally an array to accept one of parameter and copies
the real present options to a smaller variable at its end.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The A10 and A13 has a few pins that can be muxed into a particular
function that can be used as an interrupt source. Add the available
pins for such functions to the A10 and A13 description array.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The port controller IP found in the Allwinner A10 and A13 can use few of
the pins it manage as an interrupt source, called external interrupts in
the datasheet.
The number of these external interrupts are SoCs specific, but the
current upper limit is 32. In order to work, the external interrupts'
pins have to be muxed to a specific function to generate an interrupt.
This patch adds the irqchip and the needed logic to use the PIO
controller as an interrupt controller.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Avoid to use expensive string manipulation functions and search by pin
id when possible.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch fixes issues reported by prevent tool.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
[Drop hunk already in-tree from a patch by Wei Yongjun]
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Take care to name pin names as
register-offset.bit-pos-of-pin-in-register in case configuring multiple
pins in register.
Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add support to configure multiple pins in each register, existing
implementation added by [1] does not support full fledge multiple pin
configuration in single register, reports a pin clash when different
modules configure different bits of same register. The issue reported
and discussed here
http://www.spinics.net/lists/arm-kernel/msg235213.html
With pinctrl-single,bits-per-mux property specified, use function-mask
property to find out number pins to configure. Allocate and register
pin control functions based sub mask.
Tested on da850/omap-l138 EVM.
does not support variable submask for pins.
does not support pinconf.
[1] "pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux"
(9e605cb68a),
Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com>
Reported-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Tested-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If a device have sleep and idle states in addition to the
default state, look up these in the core and stash them in
the pinctrl state container.
Add accessor functions for pinctrl consumers to put the pins
into "default", "sleep" and "idle" states passing nothing but
the struct device * affected.
Solution suggested by Kevin Hilman, Mark Brown and Dmitry
Torokhov in response to a patch series from Hebbar
Gururaja.
Cc: Hebbar Gururaja <gururaja.hebbar@ti.com>
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There exist controllers that don't support to set the pull to up or down
separately but instead automatically set the pull direction based on
embedded knowledge inside the controller, for example depending on the
selected mux function of the pin.
Therefore this patch adds another config option to use this default
pull-state for a pin where it is not possible to know or decide if the
pin will be pulled up or down.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
