- Made changes to check the flash controller status before IOC initialization.
- Made changes to poll on the FLASH_STS_REG bit to check if the flash controller
initialization is completed during the PLL init.
Signed-off-by: Vijaya Mohan Guvva <vmohan@brocade.com>
Signed-off-by: Krishna Gudipati <kgudipat@brocade.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
Made changes to resume the flash controller if it is halted before going
ahead with flash controller pause/resume logic.
Made changes to avoid clearing off the interrupts during the initial
pll initialization.
Signed-off-by: Krishna Gudipati <kgudipat@brocade.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
- If flash controller is halted unconditionally, this results in
illegal write access to flash controller register domain. Since
flash controller registers are only accessible once s_clk is started
- added logic to check for WGN status and halt flash controller only
if it is already running.
- Added check to wait for flash controller halt to be completed before
proceeding with s_clk/l_clk initializations.
- Removed unnecessary reset logic for PMM 1T memory and moved memory
initialization after flash access enable.
- Disable Brocade-1860 asic MBOX interrupt before PLL initialization.
- Remove reset enable for S_CLK/L_CLK after both PLL initializations
are complete.
Signed-off-by: Krishna Gudipati <kgudipat@brocade.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
- Added support for 16Gbps.
- Added logic to flush pending mailbox command queue when IOC is disabled.
- Fix to Halt the flash controller during fw initialization - since
when asic blck is programmed flash controller's continuous access
blocks f/w access to flash.
- Added new asic based card types and modified IOC get card model routine.
- Added PLL init fix to do LPU reset every time we do a memory
initialization, since not doing so will cause LPU to be
uninitialized during driver load.
- Added fix to Halt flash controller before PLL initialization.
Signed-off-by: Krishna Gudipati <kgudipat@brocade.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
- Introduced IOC poll mechanism which replaces current interrupt
based FW READY method.
- The timer based poll routine in IOC will query the ioc_fwstate
register to see if there is a state change in FW, and sends the READY event.
- Bug fixes in the new asic PLL initialization.
- Added logic to handle CPE/RME queue interrupts before iocfc config done.
1. Use the queue_process flag to see if iocfc configuration is done
in INTX mode.
2. Split the MSIX handler installation in two - one for IOC intr
handler and the other for cpe/rme queue handler - and delay
assigning queue handlers until iocfc config is done in MSIX mode.
Signed-off-by: Krishna Gudipati <kgudipat@brocade.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
- Added support for Brocade-1860 Fabric Adapter.
- Made changes to support single firmware image per asic type.
- Combined bfi_cbreg.h and bfi_ctreg.h defines into bfi_reg.h with
only minimal defines used by host.
- Added changes to setup CPE/RME Queue register offsets based on
firmware response.
- Removed queue register offset initializations and added register offsets
to BFI config response message.
- Added Brocade-1860 asic specific interrupt status definitions and
mailbox interfaces.
Signed-off-by: Krishna Gudipati <kgudipat@brocade.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
