Because of recent changes to transfer handling on
DWC3, we will not get XferComplete unless we
completely fill up our TRB ring. This means that we
might get a Reset or Disconnect without getting a
XferComplete first.
In order to correctly release our allocated Transfer
Resource, we must issue ENDTRANSFER command whenever
dep->resource_index is valid.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
If there is a failure after pm_runtime_enable/get_sync()
we need to call pm_runtime_disable/put_sync().
Otherwise it will lead to an unbalanced pm_runtime_enable() on the
subsequent probe if the earlier probe bailed out due to -EPROBE_DEFER.
pm_runtime_get_sync() can fail as well so deal with that case too.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
it's clear now that when is_on=true, we must loop
until DWC3_DSTS_DEVCTRLHLT clears; while when
is_on=false we must loop until DWC3_DSTS_DEVCTRLHLT
gets set.
Instead of adding actual if() statements, we can
rely on XOR operation to evaluate to true only when
the above conditions apply. Then, we can move the
break condition back to the while() statement
together with our timeout check and the resulting
code is very compact and simpler to read.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
instead of looping forever and forcing a return if
timeout reaches zero, we can just use timeout and
loop's break condition directly.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
testing shows that udelay() is unnecessary as
controller reaches Halted state almost
instantenously as can be seen by our timeout
variable never actually decrementing.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
We shouldn't change a host-only dwc3 to gadget-only
if driver is built as gadget-only. Fix that up here.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
It's know that Intel's SoCs' dwc3 integration is
peripheral-only since Intel implements its own
portmux for role-swapping. In order to prevent dwc3
from ever registering and XHCI platform_device,
let's just set dr-mode to peripheral-only on Intel
SoCs.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
'modify' is what the current action is called. Let's
rename it so it matches databook. While at that,
also make sure to add support 'init' action too.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
This new set of tracepoints will help all gadget
drivers and UDC drivers when problem appears. Note
that, in order to be able to add tracepoints to
udc-core.c we had to rename that to core.c and
statically link it with trace.c to form
udc-core.o. This is to make sure that module name
stays the same.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
instead of defining all functions as static inlines,
let's move them to udc-core and export them with
EXPORT_SYMBOL_GPL, that way we can make sure that
only GPL drivers will use them.
As a side effect, it'll be nicer to add tracepoints
to the gadget API.
While at that, also fix Kconfig dependencies to
avoid randconfig build failures.
Acked-By: Sebastian Reichel <sre@kernel.org>
Acked-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Now we can try to issue Update Transfer every time
gadget driver queues a new request. This will make
sure we keep controller's queue busy for as long as
possible.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Let's only set LST bit when we run out of space in
our TRB ring. For all other cases, we keep LST bit
unset which will prevent constant allocation and
deallocation of endpoint transfer resources.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Instead of relying on empty list of queued requests,
let's rely on the fact that we have a TRB being
processed right now.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
We will be using this information to change how we
figure out when we need LST bit. For now, just
update our counters.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
According to SNPS databook, we need to pass transfer
resource on update transfer command, let's do it.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
No more users for it.
Tested-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
This should allow the core driver to drop handling of
platform data and expect the platform specific details to
always come from properties.
Tested-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Cc: Huang Rui <ray.huang@amd.com>
CC: John Youn <John.Youn@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
when passing strings to trace, we don't need the
trailing newline character. Trace already appends a
newline character automatically.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Don't make any decisions regarding VBUS session based on ID
status. That is best left to the OTG core.
Pass ID and VBUS events independent of each other so that OTG
core knows exactly what to do.
This makes dual-role with extcon work with OTG irq on OMAP platforms.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
TRM [1] recommends that POWERPRESENT bit must not be
set and left at it's default value of 0.
[1] OMAP542x TRM - http://www.ti.com/lit/pdf/swpu249
Section 23.11.4.5.1 Mailbox VBUS/ID Management
"Because PIPE powerpresent has a different meaning in host and in device mode,
and because of the redundancy with the UTMI signals, the controller ORes
together the appropriate PIPE and UTMI inputs to create its internal
VBUS status. For that reason, it is recommended to leave field
USBOTGSS_UTMI_OTG_STATUS[9] POWERPRESENT at its default value (=0), and only to
fill in the USB2 VBUS status fields in the same register."
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
On OMAPs, OTG events come on the same IRQ so we need to share
this IRQ with the OTG device driver.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
We intend to share this interrupt with the OTG driver an to ensure
that irqflags match for the shared interrupt handlers we use
request_threaded_irq()
If we don't use request_treaded_irq() then forced threaded irq will
set IRQF_ONESHOT and this won't match with the OTG IRQ handler's
IRQ flags.
NOTE: OTG IRQ handler is yet to be added. This is a preparatory step.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
GUCTL1 reg has some useful functions which can be
written by user. For rockchip platform, we set
GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK (bit26, applicable
for the core is programmed to operate in 2.0 device
only) to 1 in bootrom, and after start the kernel,
we want to check whether this bit can be reset to
default 0 after the core reset. Dump GUCTL1 reg from
debugfs is more convenient for us.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
The DWC3_USB31_REVISION_110A macro uses an invalid constant name in its
definition. This is currently not used.
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Correct the use of the DWC3_DSTS_XXX_SPEED and DWC3_DCFG_XXX_SPEED
macros. The wrong set of macros were being used in a few places.
This is only a cosmetic change as the values for both sets are
identical.
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
From sparse:
warning: cast truncates bits from constant value (100 becomes 0)
The DWC3_TRB_NUM constant is too big for u8. Do the calculation a
slightly different way that should still be optimized out for the case
where DWC3_TRB_NUM == 256.
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
If the trb->enqueue == trb->dequeue, then it could be full or empty.
This could also happen at TRB index 0, so modify the check to handle
that condition. At index 0, the previous TRB is the one just before the
link TRB.
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
The TRBs left calculation didn't account for the link TRB taking up one
spot.
If the trb_dequeue < trb_enqueue, then the result includes the link
TRB slot so it must be adjusted.
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
The current calculation takes dep->trb_dequeue - dep->trb_enqueue to
find the TRB space left.
If you enqueue 1, that results in:
(u8) 0 - (u8) 1 = 0xff = 255 TRBs left.
This is correct if DWC3_TRB_NUM == 256.
If DWC3_TRB_NUM is less than 256 (but still a power of 2) you need to
mod the result by DWC3_TRB_NUM.
For example the same calculation with DWC3_TRB_NUM = 8, results in:
255 % 6 = 7 TRBs left.
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
If trbs_left == 0, we don't have any space left in the TRB ring so don't
prepare anything.
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Clears out all the TRBs in the ring to clean up any stale data that
might be in them from the previous time the endpoint was enabled.
Also removed the existing clear of the LINK trb since the entire ring is
cleard just before.
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Make the skipping of the link TRBS built-in to the increment operation.
This simplifies the code wherever we increment the trb index and ensures
that we never end up pointing to a link trb.
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Sparse complains even though it looks ok. Probably it cannot detect that
the wValue, wIndex, and wLength are declared __le16 due to the macro
magic.
Redeclare them as CPU endianness and make the conversion on assignment.
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Cleans up the sparse warning:
warning: dubious: x | !y
Since we do want a bitwise OR here, don't use a logical (true/false)
value. Probably is not a real issue but it cleans up the warning.
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
u2sel and u2pel should be __le16. Doesn't fix any issue.
Found with sparse.
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
The wIndex passed in here is CPU endianness, but the function expects
little endian.
Found with sparse.
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Just like we did for endpoint commands, let's have a
single trace output for the command and its
status. This will improve trace readability
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Just like we did for endpoint commands, let's use a
single return point for generic commands as
well. This aids readability.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Instead of printing command's status with a separate
trace printout, let's print it within a single call.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
instead of having infinite loop and always checking
timeout value as a break condition, we can just
decrement timeout inside while's condition.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
I really thought this would be useful, but as it
turns out, it creates more problems than fixes. The
amount of times we had to fix this because some
other commit shuffled things around and ended up
regressing this tiny little string manupulation...
Might as well remove it, since it has a negligible
added benefit.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Improve trb tracing by showing trb flags, interrupts
trb type.
trb flags:
- h - hardware owner of descriptor
- l - last TRB
- c - chain buffers
- s - continue on short packet
interrupt flags:
- s - interrupt on short packet
- c - interrupt on complete
Capital letter means that bit is set, while
lowercase letter means bit is cleared.
Signed-off-by: Janusz Dziedzic <januszx.dziedzic@linux.intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
This will allow us to process several endpoints at a
time by making sure that we lock only shared
resources.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Allow for dwc3-pci to reach D3 and enable pm_runtime
by providing dummy PM hooks. Without them, PCI
subsystem won't put device to D3.
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
this patch implements the most basic pm_runtime
support for dwc3. Whenever USB cable is dettached,
then we will allow core to runtime_suspend.
Runtime suspending will involve completely tearing
down event buffers and require a full soft-reset of
the IP.
Note that a further optimization could be
implemented once we decide to support hibernation,
which is to allow runtime_suspend with cable
connected when bus is in U3. That's subject to a
separate patch, however.
Tested-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
