- fix locking issues in ISS network driver;
- document PIC and MX interrupt distributor device tree bindings;
- add CY7C67300 USB controller support to XTFPGA.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVK2UPAAoJEFH5zJH4P6BEtdEQAJpThJvrVr+Wn0BkgnSZoA3I
jRKhIwj+3c8XXcRRY+4T/hU+9Rh7+XhKjTy+u4Rbgbm5bhmvjvbwuDRS+czsa/RC
r/FE874QZD5O8KLtdqkTkyRJ4XmKDQHbDUpTuk300xQeV53fFwa6EeOclVrmZMzz
yBDaFG4rmPa7/4TTvbyLwloA355pbKuhAFT2ndRFFHty4KrfE/XZcKQk25ubgTak
PYgBGfUpyZ0F7WZ92L8F3WYcud0p4PlYXelQDVVa5iJDLQGkyrJAzDx8e+URVI+E
ym9SWVUD33kAhXwQ2i3vm7HEDD4JZJbMZQupWKHy6aqFeaXv31tU5KDOu0V3148O
9ezrAU5Ciav9NGUDQ9318Rb3cJkYoPelHWE5QHEU60VOOt4UHw3wsBtcuCnUSODl
BllotRHXYFoBsWcwOBgH1j36wsOGTKxn98wRdHvCLqD6vwneKCv8WRRNRU2N0jvB
VTVL4AOPDLmoiwcqomcSXes16ZKU98fgvbSdaCqojDDtYpsj6bsrs67joPwp9+5j
3HA3+47Hn4uaoFiDbs5N/oLgv+fFUY83o6LwxtAAufF2U92KZEX99zayQ0wB54+C
U1KR8lmXJcl2KjDXY6tGmfyXrBCwxFk2/WqN43yvvLSxDtDUtDJAw3SHCtQG6Hcd
HZFasgLoxxphwtuAkWny
=sZxq
-----END PGP SIGNATURE-----
Merge tag 'xtensa-for-next-20150413' of git://github.com/jcmvbkbc/linux-xtensa into for_next
Xtensa improvements for 4.1:
- fix locking issues in ISS network driver;
- document PIC and MX interrupt distributor device tree bindings;
- add CY7C67300 USB controller support to XTFPGA.
Signed-off-by: Chris Zankel <chris@zankel.net>
LCD driver is always built for the XTFPGA platform, but its base address
is not configurable, and is wrong for ML605/KC705. Its initialization
locks up KC705 board hardware.
Make the whole driver optional, and its base address and bus width
configurable. Implement 4-bit bus access method.
Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Connect xtfpga board ethernet MAC to the clock in the DTS. Set up MAC
base frequency in the platform data in case of build w/o CONFIG_OF.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
With this change the board needs to set up single clock object, users of
this clock will get correct frequency automatically.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Remove __initdata attribute, as the devices may be used after init
sections are freed.
Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
The recommended compatible string format, according to the ePAPR v1.1 standard,
is "manufacturer,model". Change the xtensa cpu compatible strings to
"cdns,xtensa-cpu". Also, change the boards compatible strings in a similar way.
The pic compatible string will be dealt with in a separate patch.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This is largely based on SMP code from the xtensa-2.6.29-smp tree by
Piet Delaney, Marc Gauthier, Joe Taylor, Christian Zankel (and possibly
other Tensilica folks).
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
These definitions (-1) were correct when used as a hardware IRQ number,
but are incorrect as a mapped IRQ number.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
platform_calibrate_ccount() calls update_clock_frequency() which is in .init
section. However, platform_calibrate_ccount() itself is only called from .init
(i.e., time_init()).
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
Only set the register when there is at least one ibreak register,
otherwise the build fails:
arch/xtensa/kernel/head.S:105: Error: invalid register 'ibreakenable'
for 'wsr' instruction
arch/xtensa/platforms/iss/setup.c:67: Error: invalid register
'ibreakenable' for 'wsr' instruction
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
This rename happened in 79d1c71 powerpc+of: Rename the drivers/of prom_*
functions to of_*.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
The last byte of the mac address is determined by a DIP switch, so
update the OF property with that address.
Signed-off-by: Chris Zankel <chris@zankel.net>
The Avnet LX60/LX110/LX200 board is an FPGA board that can be configured with
an Xtensa processor and an OpenCores Ethernet device.
Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
