3 Commits

Author	SHA1	Message	Date
Naveen Krishna Chatradhi	5b73721b60	clk: samsung: exynos5250/5420: Add gate clock for SSS module ... This patch adds gating clock for SSS(Security SubSystem) module on Exynos5250/5420. Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> [t.figa: Fixed sort order and group name.] Signed-off-by: Tomasz Figa <t.figa@samsung.com>	2014-05-14 19:23:26 +02:00
Andrew Bresticker	35399dda01	clk: exynos5250: add clock ID for div_pcm0 ... There is no gate for the PCM clock input to the AudioSS block, so the parent of sclk_pcm is div_pcm0. Add a clock ID for it so that we can reference it in device trees. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>	2014-01-08 18:02:42 +01:00
Andrzej Hajda	b568059b16	ARM: exynos5250: create a DT header defining CLK IDs ... The patch adds header file defining clock IDs. This allows to use macros instead of magic numbers in DT bindings. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>	2014-01-08 18:02:38 +01:00