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https://github.com/edk2-porting/linux-next.git
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net: macb: Add 64 bit addressing support for GEM
This patch adds support for 64 bit addressing and BDs. -> Enable 64 bit addressing in DMACFG register. -> Set DMA mask when design config register shows support for 64 bit addr. -> Add new BD words for higher address when 64 bit DMA support is present. -> Add and update TBQPH and RBQPH for MSB of BD pointers. -> Change extraction and updation of buffer addresses to use 64 bit address. -> In gem_rx extract address in one place insted of two and use a separate flag for RXUSED. Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Harini Katakam
David S. Miller
parent
054c67d1c8
commit
fff8019a08
@ -541,6 +541,14 @@ static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
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}
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}
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static inline void macb_set_addr(struct macb_dma_desc *desc, dma_addr_t addr)
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{
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desc->addr = (u32)addr;
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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desc->addrh = (u32)(addr >> 32);
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#endif
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}
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static void macb_tx_error_task(struct work_struct *work)
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{
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struct macb_queue *queue = container_of(work, struct macb_queue,
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@ -621,14 +629,17 @@ static void macb_tx_error_task(struct work_struct *work)
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/* Set end of TX queue */
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desc = macb_tx_desc(queue, 0);
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desc->addr = 0;
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macb_set_addr(desc, 0);
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desc->ctrl = MACB_BIT(TX_USED);
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/* Make descriptor updates visible to hardware */
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wmb();
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/* Reinitialize the TX desc queue */
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queue_writel(queue, TBQP, queue->tx_ring_dma);
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queue_writel(queue, TBQP, (u32)(queue->tx_ring_dma));
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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queue_writel(queue, TBQPH, (u32)(queue->tx_ring_dma >> 32));
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#endif
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/* Make TX ring reflect state of hardware */
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queue->tx_head = 0;
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queue->tx_tail = 0;
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@ -750,7 +761,7 @@ static void gem_rx_refill(struct macb *bp)
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if (entry == RX_RING_SIZE - 1)
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paddr |= MACB_BIT(RX_WRAP);
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bp->rx_ring[entry].addr = paddr;
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macb_set_addr(&(bp->rx_ring[entry]), paddr);
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bp->rx_ring[entry].ctrl = 0;
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/* properly align Ethernet header */
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@ -798,7 +809,9 @@ static int gem_rx(struct macb *bp, int budget)
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int count = 0;
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while (count < budget) {
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u32 addr, ctrl;
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u32 ctrl;
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dma_addr_t addr;
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bool rxused;
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entry = macb_rx_ring_wrap(bp->rx_tail);
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desc = &bp->rx_ring[entry];
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@ -806,10 +819,14 @@ static int gem_rx(struct macb *bp, int budget)
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/* Make hw descriptor updates visible to CPU */
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rmb();
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addr = desc->addr;
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rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
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addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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addr |= ((u64)(desc->addrh) << 32);
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#endif
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ctrl = desc->ctrl;
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if (!(addr & MACB_BIT(RX_USED)))
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if (!rxused)
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break;
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bp->rx_tail++;
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@ -835,7 +852,6 @@ static int gem_rx(struct macb *bp, int budget)
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netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
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skb_put(skb, len);
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addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
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dma_unmap_single(&bp->pdev->dev, addr,
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bp->rx_buffer_size, DMA_FROM_DEVICE);
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@ -1299,7 +1315,7 @@ static unsigned int macb_tx_map(struct macb *bp,
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ctrl |= MACB_BIT(TX_WRAP);
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/* Set TX buffer descriptor */
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desc->addr = tx_skb->mapping;
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macb_set_addr(desc, tx_skb->mapping);
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/* desc->addr must be visible to hardware before clearing
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* 'TX_USED' bit in desc->ctrl.
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*/
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@ -1422,6 +1438,9 @@ static void gem_free_rx_buffers(struct macb *bp)
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desc = &bp->rx_ring[i];
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addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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addr |= ((u64)(desc->addrh) << 32);
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#endif
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dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
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DMA_FROM_DEVICE);
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dev_kfree_skb_any(skb);
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@ -1547,7 +1566,7 @@ static void gem_init_rings(struct macb *bp)
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for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
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for (i = 0; i < TX_RING_SIZE; i++) {
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queue->tx_ring[i].addr = 0;
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macb_set_addr(&(queue->tx_ring[i]), 0);
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queue->tx_ring[i].ctrl = MACB_BIT(TX_USED);
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}
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queue->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
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@ -1694,6 +1713,10 @@ static void macb_configure_dma(struct macb *bp)
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dmacfg |= GEM_BIT(TXCOEN);
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else
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dmacfg &= ~GEM_BIT(TXCOEN);
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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dmacfg |= GEM_BIT(ADDR64);
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#endif
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netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
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dmacfg);
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gem_writel(bp, DMACFG, dmacfg);
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@ -1739,9 +1762,15 @@ static void macb_init_hw(struct macb *bp)
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macb_configure_dma(bp);
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/* Initialize TX and RX buffers */
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macb_writel(bp, RBQP, bp->rx_ring_dma);
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macb_writel(bp, RBQP, (u32)(bp->rx_ring_dma));
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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macb_writel(bp, RBQPH, (u32)(bp->rx_ring_dma >> 32));
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#endif
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for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
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queue_writel(queue, TBQP, queue->tx_ring_dma);
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queue_writel(queue, TBQP, (u32)(queue->tx_ring_dma));
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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queue_writel(queue, TBQPH, (u32)(queue->tx_ring_dma >> 32));
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#endif
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/* Enable interrupts */
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queue_writel(queue, IER,
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@ -2379,6 +2408,9 @@ static int macb_init(struct platform_device *pdev)
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queue->IDR = GEM_IDR(hw_q - 1);
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queue->IMR = GEM_IMR(hw_q - 1);
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queue->TBQP = GEM_TBQP(hw_q - 1);
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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queue->TBQPH = GEM_TBQPH(hw_q -1);
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#endif
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} else {
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/* queue0 uses legacy registers */
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queue->ISR = MACB_ISR;
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@ -2386,6 +2418,9 @@ static int macb_init(struct platform_device *pdev)
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queue->IDR = MACB_IDR;
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queue->IMR = MACB_IMR;
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queue->TBQP = MACB_TBQP;
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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queue->TBQPH = MACB_TBQPH;
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#endif
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}
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/* get irq: here we use the linux queue index, not the hardware
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@ -2935,6 +2970,11 @@ static int macb_probe(struct platform_device *pdev)
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bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
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device_init_wakeup(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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if (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1)) > GEM_DBW32)
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dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
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#endif
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spin_lock_init(&bp->lock);
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/* setup capabilities */
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@ -66,6 +66,8 @@
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#define MACB_USRIO 0x00c0
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#define MACB_WOL 0x00c4
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#define MACB_MID 0x00fc
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#define MACB_TBQPH 0x04C8
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#define MACB_RBQPH 0x04D4
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/* GEM register offsets. */
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#define GEM_NCFGR 0x0004 /* Network Config */
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@ -139,6 +141,7 @@
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#define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
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#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
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#define GEM_TBQPH(hw_q) (0x04C8)
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#define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
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#define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
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#define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
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@ -249,6 +252,8 @@
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#define GEM_RXBS_SIZE 8
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#define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
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#define GEM_DDRP_SIZE 1
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#define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */
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#define GEM_ADDR64_SIZE 1
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/* Bitfields in NSR */
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@ -474,6 +479,10 @@
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struct macb_dma_desc {
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u32 addr;
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u32 ctrl;
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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u32 addrh;
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u32 resvd;
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#endif
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};
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/* DMA descriptor bitfields */
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@ -777,6 +786,7 @@ struct macb_queue {
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unsigned int IDR;
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unsigned int IMR;
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unsigned int TBQP;
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unsigned int TBQPH;
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unsigned int tx_head, tx_tail;
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struct macb_dma_desc *tx_ring;
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