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Code

ARM: dts: rockchip: oder nodes by register address

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To create some sort of ordering of nodes, they are suggested to be ordered by
their register address.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Heiko Stuebner 2014-07-26 23:28:03 +02:00
parent 6e4b3b4b66
commit ff84b90ecd
2 changed files with 67 additions and 67 deletions
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48
arch/arm/boot/dts/rk3066a.dtsi
View File

@ -40,30 +40,6 @@
}; };
}; };
timer@20038000 {
compatible = "snps,dw-apb-timer-osc";
reg = <0x20038000 0x100>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
clock-names = "timer", "pclk";
};
timer@2003a000 {
compatible = "snps,dw-apb-timer-osc";
reg = <0x2003a000 0x100>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
clock-names = "timer", "pclk";
};
timer@2000e000 {
compatible = "snps,dw-apb-timer-osc";
reg = <0x2000e000 0x100>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
clock-names = "timer", "pclk";
};
sram: sram@10080000 { sram: sram@10080000 {
compatible = "mmio-sram"; compatible = "mmio-sram";
reg = <0x10080000 0x10000>; reg = <0x10080000 0x10000>;
@ -86,6 +62,30 @@
#reset-cells = <1>; #reset-cells = <1>;
}; };
timer@2000e000 {
compatible = "snps,dw-apb-timer-osc";
reg = <0x2000e000 0x100>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
clock-names = "timer", "pclk";
};
timer@20038000 {
compatible = "snps,dw-apb-timer-osc";
reg = <0x20038000 0x100>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
clock-names = "timer", "pclk";
};
timer@2003a000 {
compatible = "snps,dw-apb-timer-osc";
reg = <0x2003a000 0x100>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
clock-names = "timer", "pclk";
};
pinctrl: pinctrl { pinctrl: pinctrl {
compatible = "rockchip,rk3066a-pinctrl"; compatible = "rockchip,rk3066a-pinctrl";
rockchip,grf = <&grf>; rockchip,grf = <&grf>;

86
arch/arm/boot/dts/rk3xxx.dtsi
View File

@ -27,29 +27,6 @@
clock-output-names = "xin24m"; clock-output-names = "xin24m";
}; };
scu@1013c000 {
compatible = "arm,cortex-a9-scu";
reg = <0x1013c000 0x100>;
};
pmu: pmu@20004000 {
compatible = "rockchip,rk3066-pmu", "syscon";
reg = <0x20004000 0x100>;
};
grf: grf@20008000 {
compatible = "syscon";
reg = <0x20008000 0x200>;
};
gic: interrupt-controller@1013d000 {
compatible = "arm,cortex-a9-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x1013d000 0x1000>,
<0x1013c100 0x0100>;
};
L2: l2-cache-controller@10138000 { L2: l2-cache-controller@10138000 {
compatible = "arm,pl310-cache"; compatible = "arm,pl310-cache";
reg = <0x10138000 0x1000>; reg = <0x10138000 0x1000>;
@ -57,6 +34,11 @@
cache-level = <2>; cache-level = <2>;
}; };
scu@1013c000 {
compatible = "arm,cortex-a9-scu";
reg = <0x1013c000 0x100>;
};
global_timer: global-timer@1013c200 { global_timer: global-timer@1013c200 {
compatible = "arm,cortex-a9-global-timer"; compatible = "arm,cortex-a9-global-timer";
reg = <0x1013c200 0x20>; reg = <0x1013c200 0x20>;
@ -71,6 +53,14 @@
clocks = <&cru CORE_PERI>; clocks = <&cru CORE_PERI>;
}; };
gic: interrupt-controller@1013d000 {
compatible = "arm,cortex-a9-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x1013d000 0x1000>,
<0x1013c100 0x0100>;
};
uart0: serial@10124000 { uart0: serial@10124000 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x10124000 0x400>; reg = <0x10124000 0x400>;
@ -91,26 +81,6 @@
status = "disabled"; status = "disabled";
}; };
uart2: serial@20064000 {
compatible = "snps,dw-apb-uart";
reg = <0x20064000 0x400>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
clocks = <&cru SCLK_UART2>;
status = "disabled";
};
uart3: serial@20068000 {
compatible = "snps,dw-apb-uart";
reg = <0x20068000 0x400>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
clocks = <&cru SCLK_UART3>;
status = "disabled";
};
mmc0: dwmmc@10214000 { mmc0: dwmmc@10214000 {
compatible = "rockchip,rk2928-dw-mshc"; compatible = "rockchip,rk2928-dw-mshc";
reg = <0x10214000 0x1000>; reg = <0x10214000 0x1000>;
@ -136,4 +106,34 @@
status = "disabled"; status = "disabled";
}; };
pmu: pmu@20004000 {
compatible = "rockchip,rk3066-pmu", "syscon";
reg = <0x20004000 0x100>;
};
grf: grf@20008000 {
compatible = "syscon";
reg = <0x20008000 0x200>;
};
uart2: serial@20064000 {
compatible = "snps,dw-apb-uart";
reg = <0x20064000 0x400>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
clocks = <&cru SCLK_UART2>;
status = "disabled";
};
uart3: serial@20068000 {
compatible = "snps,dw-apb-uart";
reg = <0x20068000 0x400>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <1>;
clocks = <&cru SCLK_UART3>;
status = "disabled";
};
}; };