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clk: rockchip: protect critical clocks from getting disabled
The clock-tree contains clocks that should never get disabled automatically. One example are the base ACLKs, the base supplies for all peripherals. Therefore add a structure similar to the sunxi clock-tree to protect these special clocks from being disabled. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Doug Anderson <dianders@chromium.org> Tested-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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1a4b181995
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@ -599,6 +599,11 @@ static struct rockchip_clk_branch rk3188_clk_branches[] __initdata = {
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GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
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GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
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};
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};
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static const char *rk3188_critical_clocks[] __initconst = {
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"aclk_cpu",
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"aclk_peri",
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};
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static void __init rk3188_common_clk_init(struct device_node *np)
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static void __init rk3188_common_clk_init(struct device_node *np)
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{
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{
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void __iomem *reg_base;
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void __iomem *reg_base;
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@ -628,6 +633,8 @@ static void __init rk3188_common_clk_init(struct device_node *np)
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RK3188_GRF_SOC_STATUS);
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RK3188_GRF_SOC_STATUS);
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rockchip_clk_register_branches(common_clk_branches,
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rockchip_clk_register_branches(common_clk_branches,
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ARRAY_SIZE(common_clk_branches));
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ARRAY_SIZE(common_clk_branches));
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rockchip_clk_protect_critical(rk3188_critical_clocks,
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ARRAY_SIZE(rk3188_critical_clocks));
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rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
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rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
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ROCKCHIP_SOFTRST_HIWORD_MASK);
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ROCKCHIP_SOFTRST_HIWORD_MASK);
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@ -680,6 +680,11 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
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GATE(0, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
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GATE(0, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
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};
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};
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static const char *rk3288_critical_clocks[] __initconst = {
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"aclk_cpu",
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"aclk_peri",
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};
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static void __init rk3288_clk_init(struct device_node *np)
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static void __init rk3288_clk_init(struct device_node *np)
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{
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{
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void __iomem *reg_base;
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void __iomem *reg_base;
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@ -710,6 +715,8 @@ static void __init rk3288_clk_init(struct device_node *np)
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RK3288_GRF_SOC_STATUS);
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RK3288_GRF_SOC_STATUS);
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rockchip_clk_register_branches(rk3288_clk_branches,
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rockchip_clk_register_branches(rk3288_clk_branches,
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ARRAY_SIZE(rk3288_clk_branches));
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ARRAY_SIZE(rk3288_clk_branches));
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rockchip_clk_protect_critical(rk3288_critical_clocks,
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ARRAY_SIZE(rk3288_critical_clocks));
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rockchip_register_softrst(np, 9, reg_base + RK3288_SOFTRST_CON(0),
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rockchip_register_softrst(np, 9, reg_base + RK3288_SOFTRST_CON(0),
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ROCKCHIP_SOFTRST_HIWORD_MASK);
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ROCKCHIP_SOFTRST_HIWORD_MASK);
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@ -296,3 +296,16 @@ void __init rockchip_clk_register_branches(
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rockchip_clk_add_lookup(clk, list->id);
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rockchip_clk_add_lookup(clk, list->id);
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}
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}
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}
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}
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void __init rockchip_clk_protect_critical(const char *clocks[], int nclocks)
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{
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int i;
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/* Protect the clocks that needs to stay on */
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for (i = 0; i < nclocks; i++) {
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struct clk *clk = __clk_lookup(clocks[i]);
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if (clk)
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clk_prepare_enable(clk);
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}
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}
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@ -329,6 +329,7 @@ void rockchip_clk_register_branches(struct rockchip_clk_branch *clk_list,
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unsigned int nr_clk);
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unsigned int nr_clk);
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void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list,
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void rockchip_clk_register_plls(struct rockchip_pll_clock *pll_list,
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unsigned int nr_pll, int grf_lock_offset);
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unsigned int nr_pll, int grf_lock_offset);
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void rockchip_clk_protect_critical(const char *clocks[], int nclocks);
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#define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
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#define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
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