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media: mediatek: vcodec: Read HW active status from syscon

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Remove the requirement of a VDEC_SYS reg iospace for both MT8173 and
MT8183. To achieve that, rely on a vdecsys syscon to be passed through
the DT, and use it to directly read the VDEC_HW_ACTIVE bit during IRQ
handling to check whether the HW is active. Also update the VP8 stateful
decoder to use the syscon, if present, for writes to VDEC_SYS.

The old behavior is still present when reg-names aren't supplied, as
to keep backward compatibility.

Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
[hverkuil: added vdecsys_regmap kerneldoc line provided by Nicolas]
This commit is contained in:
Nícolas F. R. A. Prado 2023-06-30 11:14:11 -04:00 committed by Hans Verkuil
parent c332621712
commit fe8a339783
5 changed files with 88 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

77
drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c
View File

@ -5,14 +5,17 @@
* Tiffany Lin <tiffany.lin@mediatek.com>
*/
#include <linux/bitfield.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <media/v4l2-event.h>
#include <media/v4l2-mem2mem.h>
#include <media/videobuf2-dma-contig.h>
@ -39,22 +42,30 @@ static int mtk_vcodec_get_hw_count(struct mtk_vcodec_dev *dev)
}
}
static bool mtk_vcodec_is_hw_active(struct mtk_vcodec_dev *dev)
{
u32 cg_status;
if (dev->vdecsys_regmap)
return !regmap_test_bits(dev->vdecsys_regmap, VDEC_HW_ACTIVE_ADDR,
VDEC_HW_ACTIVE_MASK);
cg_status = readl(dev->reg_base[VDEC_SYS] + VDEC_HW_ACTIVE_ADDR);
return !FIELD_GET(VDEC_HW_ACTIVE_MASK, cg_status);
}
static irqreturn_t mtk_vcodec_dec_irq_handler(int irq, void *priv)
{
struct mtk_vcodec_dev *dev = priv;
struct mtk_vcodec_ctx *ctx;
u32 cg_status = 0;
unsigned int dec_done_status = 0;
void __iomem *vdec_misc_addr = dev->reg_base[VDEC_MISC] +
VDEC_IRQ_CFG_REG;
ctx = mtk_vcodec_get_curr_ctx(dev, MTK_VDEC_CORE);
/* check if HW active or not */
cg_status = readl(dev->reg_base[0] + VDEC_HW_ACTIVE_ADDR);
if ((cg_status & VDEC_HW_ACTIVE_MASK) != 0) {
mtk_v4l2_err("DEC ISR, VDEC active is not 0x0 (0x%08x)",
cg_status);
if (!mtk_vcodec_is_hw_active(dev)) {
mtk_v4l2_err("DEC ISR, VDEC active is not 0x0");
return IRQ_HANDLED;
}
@ -83,6 +94,33 @@ static int mtk_vcodec_get_reg_bases(struct mtk_vcodec_dev *dev)
{
struct platform_device *pdev = dev->plat_dev;
int reg_num, i;
struct resource *res;
bool has_vdecsys_reg;
static const char * const mtk_dec_reg_names[] = {
"misc",
"ld",
"top",
"cm",
"ad",
"av",
"pp",
"hwd",
"hwq",
"hwb",
"hwg"
};
/*
* If we have reg-names in devicetree, this means that we're on a new
* register organization, which implies that the VDEC_SYS iospace gets
* R/W through a syscon (regmap).
* Here we try to get the "misc" iostart only to check if we have reg-names
*/
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "misc");
if (res)
has_vdecsys_reg = false;
else
has_vdecsys_reg = true;
/* Sizeof(u32) * 4 bytes for each register base. */
reg_num = of_property_count_elems_of_size(pdev->dev.of_node, "reg",
@ -92,12 +130,29 @@ static int mtk_vcodec_get_reg_bases(struct mtk_vcodec_dev *dev)
return -EINVAL;
}
for (i = 0; i < reg_num; i++) {
dev->reg_base[i] = devm_platform_ioremap_resource(pdev, i);
if (IS_ERR(dev->reg_base[i]))
return PTR_ERR(dev->reg_base[i]);
if (has_vdecsys_reg) {
for (i = 0; i < reg_num; i++) {
dev->reg_base[i] = devm_platform_ioremap_resource(pdev, i);
if (IS_ERR(dev->reg_base[i]))
return PTR_ERR(dev->reg_base[i]);
mtk_v4l2_debug(2, "reg[%d] base=%p", i, dev->reg_base[i]);
mtk_v4l2_debug(2, "reg[%d] base=%p", i, dev->reg_base[i]);
}
} else {
for (i = 0; i < reg_num; i++) {
dev->reg_base[i+1] = devm_platform_ioremap_resource_byname(pdev, mtk_dec_reg_names[i]);
if (IS_ERR(dev->reg_base[i+1]))
return PTR_ERR(dev->reg_base[i+1]);
mtk_v4l2_debug(2, "reg[%d] base=%p", i+1, dev->reg_base[i+1]);
}
dev->vdecsys_regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
"mediatek,vdecsys");
if (IS_ERR(dev->vdecsys_regmap)) {
dev_err(&pdev->dev, "Missing mediatek,vdecsys property");
return PTR_ERR(dev->vdecsys_regmap);
}
}
return 0;

2
drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h
View File

@ -441,6 +441,7 @@ struct mtk_vcodec_enc_pdata {
* @reg_base: Mapped address of MTK Vcodec registers.
* @vdec_pdata: decoder IC-specific data
* @venc_pdata: encoder IC-specific data
* @vdecsys_regmap: VDEC_SYS register space passed through syscon
*
* @fw_handler: used to communicate with the firmware.
* @id_counter: used to identify current opened instance
@ -489,6 +490,7 @@ struct mtk_vcodec_dev {
void __iomem *reg_base[NUM_MAX_VCODEC_REG_BASE];
const struct mtk_vcodec_dec_pdata *vdec_pdata;
const struct mtk_vcodec_enc_pdata *venc_pdata;
struct regmap *vdecsys_regmap;
struct mtk_vcodec_fw *fw_handler;

15
drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.c
View File

@ -7,6 +7,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regmap.h>
#include "mtk_vcodec_dec_hw.h"
#include "mtk_vcodec_drv.h"
@ -33,6 +34,20 @@ void __iomem *mtk_vcodec_get_reg_addr(struct mtk_vcodec_ctx *data,
}
EXPORT_SYMBOL(mtk_vcodec_get_reg_addr);
int mtk_vcodec_write_vdecsys(struct mtk_vcodec_ctx *ctx, unsigned int reg,
unsigned int val)
{
struct mtk_vcodec_dev *dev = ctx->dev;
if (dev->vdecsys_regmap)
return regmap_write(dev->vdecsys_regmap, reg, val);
writel(val, dev->reg_base[VDEC_SYS] + reg);
return 0;
}
EXPORT_SYMBOL(mtk_vcodec_write_vdecsys);
int mtk_vcodec_mem_alloc(struct mtk_vcodec_ctx *data,
struct mtk_vcodec_mem *mem)
{

2
drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.h
View File

@ -70,6 +70,8 @@ extern int mtk_vcodec_dbg;
void __iomem *mtk_vcodec_get_reg_addr(struct mtk_vcodec_ctx *data,
unsigned int reg_idx);
int mtk_vcodec_write_vdecsys(struct mtk_vcodec_ctx *ctx, unsigned int reg,
unsigned int val);
int mtk_vcodec_mem_alloc(struct mtk_vcodec_ctx *data,
struct mtk_vcodec_mem *mem);
void mtk_vcodec_mem_free(struct mtk_vcodec_ctx *data,

10
drivers/media/platform/mediatek/vcodec/vdec/vdec_vp8_if.c
View File

@ -91,7 +91,6 @@ struct vdec_vp8_vsi {
/**
* struct vdec_vp8_hw_reg_base - HW register base
* @sys : base address for sys
* @misc : base address for misc
* @ld : base address for ld
* @top : base address for top
@ -100,7 +99,6 @@ struct vdec_vp8_vsi {
* @hwb : base address for hwb
*/
struct vdec_vp8_hw_reg_base {
void __iomem *sys;
void __iomem *misc;
void __iomem *ld;
void __iomem *top;
@ -170,7 +168,6 @@ static void get_hw_reg_base(struct vdec_vp8_inst *inst)
inst->reg_base.top = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_TOP);
inst->reg_base.cm = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_CM);
inst->reg_base.hwd = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_HWD);
inst->reg_base.sys = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_SYS);
inst->reg_base.misc = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_MISC);
inst->reg_base.ld = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_LD);
inst->reg_base.hwb = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_HWB);
@ -222,17 +219,16 @@ static void read_hw_segmentation_data(struct vdec_vp8_inst *inst)
static void enable_hw_rw_function(struct vdec_vp8_inst *inst)
{
u32 val = 0;
void __iomem *sys = inst->reg_base.sys;
void __iomem *misc = inst->reg_base.misc;
void __iomem *ld = inst->reg_base.ld;
void __iomem *hwb = inst->reg_base.hwb;
void __iomem *hwd = inst->reg_base.hwd;
writel(0x1, sys + VP8_RW_CKEN_SET);
mtk_vcodec_write_vdecsys(inst->ctx, VP8_RW_CKEN_SET, 0x1);
writel(0x101, ld + VP8_WO_VLD_SRST);
writel(0x101, hwb + VP8_WO_VLD_SRST);
writel(1, sys);
mtk_vcodec_write_vdecsys(inst->ctx, 0, 0x1);
val = readl(misc + VP8_RW_MISC_SRST);
writel((val & 0xFFFFFFFE), misc + VP8_RW_MISC_SRST);
@ -241,7 +237,7 @@ static void enable_hw_rw_function(struct vdec_vp8_inst *inst)
writel(0x71201100, misc + VP8_RW_MISC_FUNC_CON);
writel(0x0, ld + VP8_WO_VLD_SRST);
writel(0x0, hwb + VP8_WO_VLD_SRST);
writel(0x1, sys + VP8_RW_DCM_CON);
mtk_vcodec_write_vdecsys(inst->ctx, VP8_RW_DCM_CON, 0x1);
writel(0x1, misc + VP8_RW_MISC_DCM_CON);
writel(0x1, hwd + VP8_RW_VP8_CTRL);
}