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IB/mlx5: Fix alignment of reg umr gather buffers
The hardware requires that gather buffers for UMR work requests be aligned to 2K. Signed-off-by: Eli Cohen <eli@mellanox.com> Signed-off-by: Roland Dreier <roland@purestorage.com>
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@ -42,6 +42,10 @@ enum {
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DEF_CACHE_SIZE = 10,
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};
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enum {
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MLX5_UMR_ALIGN = 2048
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};
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static __be64 *mr_align(__be64 *ptr, int align)
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{
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unsigned long mask = align - 1;
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@ -671,12 +675,12 @@ static struct mlx5_ib_mr *reg_umr(struct ib_pd *pd, struct ib_umem *umem,
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if (!mr)
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return ERR_PTR(-EAGAIN);
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mr->pas = kmalloc(size + 0x3f, GFP_KERNEL);
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mr->pas = kmalloc(size + MLX5_UMR_ALIGN - 1, GFP_KERNEL);
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if (!mr->pas) {
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err = -ENOMEM;
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goto error;
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}
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mr->dma = dma_map_single(ddev, mr_align(mr->pas, 0x40), size,
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mr->dma = dma_map_single(ddev, mr_align(mr->pas, MLX5_UMR_ALIGN), size,
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DMA_TO_DEVICE);
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if (dma_mapping_error(ddev, mr->dma)) {
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kfree(mr->pas);
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@ -684,7 +688,8 @@ static struct mlx5_ib_mr *reg_umr(struct ib_pd *pd, struct ib_umem *umem,
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goto error;
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}
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mlx5_ib_populate_pas(dev, umem, page_shift, mr_align(mr->pas, 0x40), 1);
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mlx5_ib_populate_pas(dev, umem, page_shift,
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mr_align(mr->pas, MLX5_UMR_ALIGN), 1);
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memset(&wr, 0, sizeof(wr));
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wr.wr_id = (u64)(unsigned long)mr;
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