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powerpc/8xx: Update TLB asm so it behaves as linux mm expects.
Update the TLB asm to make proper use of _PAGE_DIRY and _PAGE_ACCESSED.
Get rid of _PAGE_HWWRITE too.
Pros:
- I/D TLB Miss never needs to write to the linux pte.
- _PAGE_ACCESSED is only set on TLB Error fixing accounting
- _PAGE_DIRTY is mapped to 0x100, the changed bit, and is set directly
when a page has been made dirty.
- Proper RO/RW mapping of user space.
- Free up 2 SW TLB bits in the linux pte(add back _PAGE_WRITETHRU ?)
- kernel RO/user NA support.
Cons:
- A few more instructions in the TLB Miss routines.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Joakim Tjernlund
Benjamin Herrenschmidt
parent
5efab4a02c
commit
fe11dc3f96
@ -33,21 +33,20 @@
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#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
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#define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
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#define _PAGE_SPECIAL 0x0008 /* SW entry, forced to 0 by the TLB miss */
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#define _PAGE_DIRTY 0x0100 /* C: page changed */
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/* These five software bits must be masked out when the entry is loaded
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* into the TLB.
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/* These 3 software bits must be masked out when the entry is loaded
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* into the TLB, 2 SW bits left.
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*/
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#define _PAGE_GUARDED 0x0010 /* software: guarded access */
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#define _PAGE_DIRTY 0x0020 /* software: page changed */
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#define _PAGE_RW 0x0040 /* software: user write access allowed */
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#define _PAGE_ACCESSED 0x0080 /* software: page referenced */
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#define _PAGE_ACCESSED 0x0020 /* software: page referenced */
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/* Setting any bits in the nibble with the follow two controls will
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* require a TLB exception handler change. It is assumed unused bits
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* are always zero.
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*/
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#define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */
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#define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */
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#define _PAGE_RW 0x0400 /* lsb PP bits, inverted in HW */
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#define _PAGE_USER 0x0800 /* msb PP bits */
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#define _PMD_PRESENT 0x0001
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#define _PMD_BAD 0x0ff0
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@ -333,26 +333,20 @@ InstructionTLBMiss:
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mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
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lwz r10, 0(r11) /* Get the pte */
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#ifdef CONFIG_SWAP
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/* do not set the _PAGE_ACCESSED bit of a non-present page */
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andi. r11, r10, _PAGE_PRESENT
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beq 4f
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ori r10, r10, _PAGE_ACCESSED
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mfspr r11, SPRN_MD_TWC /* get the pte address again */
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stw r10, 0(r11)
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4:
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#else
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ori r10, r10, _PAGE_ACCESSED
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stw r10, 0(r11)
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#endif
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andi. r11, r10, _PAGE_ACCESSED | _PAGE_PRESENT
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cmpwi cr0, r11, _PAGE_ACCESSED | _PAGE_PRESENT
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bne- cr0, 2f
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/* Clear PP lsb, 0x400 */
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rlwinm r10, r10, 0, 22, 20
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/* The Linux PTE won't go exactly into the MMU TLB.
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* Software indicator bits 21, 22 and 28 must be clear.
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* Software indicator bits 22 and 28 must be clear.
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* Software indicator bits 24, 25, 26, and 27 must be
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* set. All other Linux PTE bits control the behavior
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* of the MMU.
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*/
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2: li r11, 0x00f0
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li r11, 0x00f0
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rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
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DO_8xx_CPU6(0x2d80, r3)
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mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
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@ -365,6 +359,22 @@ InstructionTLBMiss:
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lwz r3, 8(r0)
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#endif
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rfi
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2:
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mfspr r11, SPRN_SRR1
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/* clear all error bits as TLB Miss
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* sets a few unconditionally
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*/
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rlwinm r11, r11, 0, 0xffff
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mtspr SPRN_SRR1, r11
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mfspr r10, SPRN_M_TW /* Restore registers */
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lwz r11, 0(r0)
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mtcr r11
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lwz r11, 4(r0)
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#ifdef CONFIG_8xx_CPU6
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lwz r3, 8(r0)
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#endif
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b InstructionAccess
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. = 0x1200
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DataStoreTLBMiss:
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@ -409,21 +419,27 @@ DataStoreTLBMiss:
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DO_8xx_CPU6(0x3b80, r3)
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mtspr SPRN_MD_TWC, r11
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#ifdef CONFIG_SWAP
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/* do not set the _PAGE_ACCESSED bit of a non-present page */
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andi. r11, r10, _PAGE_PRESENT
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beq 4f
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ori r10, r10, _PAGE_ACCESSED
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4:
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/* and update pte in table */
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#else
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ori r10, r10, _PAGE_ACCESSED
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#endif
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mfspr r11, SPRN_MD_TWC /* get the pte address again */
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stw r10, 0(r11)
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/* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
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* We also need to know if the insn is a load/store, so:
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* Clear _PAGE_PRESENT and load that which will
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* trap into DTLB Error with store bit set accordinly.
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*/
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/* PRESENT=0x1, ACCESSED=0x20
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* r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
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* r10 = (r10 & ~PRESENT) | r11;
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*/
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rlwinm r11, r10, 32-5, 31, 31
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and r11, r11, r10
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rlwimi r10, r11, 0, 31, 31
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/* Honour kernel RO, User NA */
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andi. r11, r10, _PAGE_USER | _PAGE_RW
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bne- cr0, 5f
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ori r10,r10, 0x200 /* Extended encoding, bit 22 */
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5: xori r10, r10, _PAGE_RW /* invert RW bit */
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/* The Linux PTE won't go exactly into the MMU TLB.
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* Software indicator bits 21, 22 and 28 must be clear.
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* Software indicator bits 22 and 28 must be clear.
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* Software indicator bits 24, 25, 26, and 27 must be
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* set. All other Linux PTE bits control the behavior
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* of the MMU.
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@ -469,11 +485,12 @@ DataTLBError:
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stw r10, 0(r0)
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stw r11, 4(r0)
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/* First, make sure this was a store operation.
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mfspr r11, SPRN_DSISR
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andis. r11, r11, 0x4800 /* !translation or protection */
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bne 2f /* branch if either is set */
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/* Only Change bit left now, do it here as it is faster
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* than trapping to the C fault handler.
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*/
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mfspr r10, SPRN_DSISR
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andis. r11, r10, 0x0200 /* If set, indicates store op */
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beq 2f
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/* The EA of a data TLB miss is automatically stored in the MD_EPN
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* register. The EA of a data TLB error is automatically stored in
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@ -522,26 +539,12 @@ DataTLBError:
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mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
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lwz r10, 0(r11) /* Get the pte */
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andi. r11, r10, _PAGE_RW /* Is it writeable? */
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beq 2f /* Bail out if not */
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/* Update 'changed', among others.
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*/
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#ifdef CONFIG_SWAP
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ori r10, r10, _PAGE_DIRTY|_PAGE_HWWRITE
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/* do not set the _PAGE_ACCESSED bit of a non-present page */
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andi. r11, r10, _PAGE_PRESENT
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beq 4f
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ori r10, r10, _PAGE_ACCESSED
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4:
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#else
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ori r10, r10, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
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#endif
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mfspr r11, SPRN_MD_TWC /* Get pte address again */
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ori r10, r10, _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HWWRITE
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stw r10, 0(r11) /* and update pte in table */
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xori r10, r10, _PAGE_RW /* RW bit is inverted */
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/* The Linux PTE won't go exactly into the MMU TLB.
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* Software indicator bits 21, 22 and 28 must be clear.
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* Software indicator bits 22 and 28 must be clear.
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* Software indicator bits 24, 25, 26, and 27 must be
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* set. All other Linux PTE bits control the behavior
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* of the MMU.
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