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ASoC: SOF: Intel: remove the HDA_DSP_CORE_MASK() macro
Remove the HDA_DSP_CORE_MASK() macro and use BIT() and GENMASK() macros directly for more clarity. Signed-off-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Reviewed-by: Rander Wang <rander.wang@linux.intel.com> Reviewed-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com> Reviewed-by: Keyon Jie <yang.jie@linux.intel.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com> Link: https://lore.kernel.org/r/20200910164125.2033062-4-kai.vehmanen@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -129,7 +129,7 @@ const struct sof_intel_dsp_desc apl_chip_info = {
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/* Apollolake */
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.cores_num = 2,
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.init_core_mask = 1,
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.host_managed_cores_mask = HDA_DSP_CORE_MASK(0) | HDA_DSP_CORE_MASK(1),
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.host_managed_cores_mask = GENMASK(1, 0),
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.ipc_req = HDA_DSP_REG_HIPCI,
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.ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,
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.ipc_ack = HDA_DSP_REG_HIPCIE,
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@ -334,10 +334,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
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/* Cannonlake */
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.cores_num = 4,
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.init_core_mask = 1,
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.host_managed_cores_mask = HDA_DSP_CORE_MASK(0) |
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HDA_DSP_CORE_MASK(1) |
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HDA_DSP_CORE_MASK(2) |
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HDA_DSP_CORE_MASK(3),
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.host_managed_cores_mask = GENMASK(3, 0),
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.ipc_req = CNL_DSP_REG_HIPCIDR,
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
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.ipc_ack = CNL_DSP_REG_HIPCIDA,
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@ -353,10 +350,7 @@ const struct sof_intel_dsp_desc icl_chip_info = {
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/* Icelake */
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.cores_num = 4,
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.init_core_mask = 1,
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.host_managed_cores_mask = HDA_DSP_CORE_MASK(0) |
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HDA_DSP_CORE_MASK(1) |
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HDA_DSP_CORE_MASK(2) |
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HDA_DSP_CORE_MASK(3),
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.host_managed_cores_mask = GENMASK(3, 0),
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.ipc_req = CNL_DSP_REG_HIPCIDR,
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
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.ipc_ack = CNL_DSP_REG_HIPCIDA,
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@ -372,7 +366,7 @@ const struct sof_intel_dsp_desc ehl_chip_info = {
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/* Elkhartlake */
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.cores_num = 4,
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.init_core_mask = 1,
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.host_managed_cores_mask = HDA_DSP_CORE_MASK(0),
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.host_managed_cores_mask = BIT(0),
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.ipc_req = CNL_DSP_REG_HIPCIDR,
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
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.ipc_ack = CNL_DSP_REG_HIPCIDA,
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@ -388,8 +382,7 @@ const struct sof_intel_dsp_desc jsl_chip_info = {
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/* Jasperlake */
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.cores_num = 2,
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.init_core_mask = 1,
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.host_managed_cores_mask = HDA_DSP_CORE_MASK(0) |
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HDA_DSP_CORE_MASK(1),
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.host_managed_cores_mask = GENMASK(1, 0),
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.ipc_req = CNL_DSP_REG_HIPCIDR,
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
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.ipc_ack = CNL_DSP_REG_HIPCIDA,
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@ -114,7 +114,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, int iteration)
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((stream_tag - 1) << 9)));
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/* step 3: unset core 0 reset state & unstall/run core 0 */
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ret = hda_dsp_core_run(sdev, HDA_DSP_CORE_MASK(0));
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ret = hda_dsp_core_run(sdev, BIT(0));
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if (ret < 0) {
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if (iteration == HDA_FW_BOOT_ATTEMPTS)
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dev_err(sdev->dev,
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@ -146,8 +146,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, int iteration)
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chip->ipc_ack_mask);
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/* step 5: power down corex */
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ret = hda_dsp_core_power_down(sdev,
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chip->host_managed_cores_mask & ~(HDA_DSP_CORE_MASK(0)));
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ret = hda_dsp_core_power_down(sdev, chip->host_managed_cores_mask & ~(BIT(0)));
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if (ret < 0) {
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if (iteration == HDA_FW_BOOT_ATTEMPTS)
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dev_err(sdev->dev,
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@ -305,9 +305,6 @@
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#define HDA_DSP_ADSPCS_CPA_SHIFT 24
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#define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
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/* Mask for a given core index, c = 0.. number of supported cores - 1 */
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#define HDA_DSP_CORE_MASK(c) BIT(c)
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/*
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* Mask for a given number of cores
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* nc = number of supported cores
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@ -124,7 +124,7 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
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/* Tigerlake */
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.cores_num = 4,
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.init_core_mask = 1,
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.host_managed_cores_mask = HDA_DSP_CORE_MASK(0),
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.host_managed_cores_mask = BIT(0),
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.ipc_req = CNL_DSP_REG_HIPCIDR,
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.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
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.ipc_ack = CNL_DSP_REG_HIPCIDA,
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