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drm amdgpu fixes for 5.9 final
amdgpu: - Fix a crash on renoir if you override the IP discovery parameter - Fix the build on ARC platforms - Display fix for Sienna Cichlid -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJff+O4AAoJEAx081l5xIa+RTYQAIJ/AOXL1WgpUEx1z+gESGcg Vdh4/itUp0NI4UTknqb6Kx0jQAkiFWDXSe44QOyZJv/aOpv5+SJCQhudtnVx+Kgi jbhE7FKsdcxyIeKkvkK6uylzueLefqfwhrJhxCzlVwapDaR5DPjkppR2xbxVqDBu Ve/OrlCPN6Myt/O1Z98AEiTl00dMC7OIJUFHatwmguFCHtxI9JPBGz/qvMCtzltm HO9DoPyPFamJhEkAzkIru5Rwk6F9JB2A27FES9vP9l2ERY34yhjx3rLaYVjywdhu K7xaVWPtm2jbTWqEF/GsmXf0WEqJWEakEDVGIRpyyhTnWC/vhlMjX3W3sZstR49u h/qN6PA0GDoNoAsd6ldRo+Ey8DudZ/UDY49FXO86cIiT6IJFLWG01bm9fzDWOdQg V/iqcU8jf3xC2Wsb2fUodbvMvvaoR1HeBjseYL5EWKvJpux905pgJS7IzepGvZct 67ObfhS+3bqW1hPU18OmZlth/mAZOw5FtYFforMsyAbNHAFKNQ65OjYk/jmpM2I3 P0m03/v1hTgneTIwa0HO9/XuWDERv7Ay/Z5niD8OwSRLUXDAEYrAGqgNosbYDu29 bX1BEhUQLclUcBCJbzSjwu7WlQzElGdNVU+AAbtlhr/HeLhxYEh9iZDAUUgxWsID G2/kaJBywsmIrdVFU5uN =EI05 -----END PGP SIGNATURE----- Merge tag 'drm-fixes-2020-10-09' of git://anongit.freedesktop.org/drm/drm Pull amdgpu drm fixes from Dave Airlie: "Fixes trickling in this week. Alex had a final fix for the newest GPU they introduced in rc1, along with one build regression and one crasher fix. Cross my fingers that's it for 5.9: - Fix a crash on renoir if you override the IP discovery parameter - Fix the build on ARC platforms - Display fix for Sienna Cichlid" * tag 'drm-fixes-2020-10-09' of git://anongit.freedesktop.org/drm/drm: drm/amd/display: Change ABM config init interface drm/amdgpu/swsmu: fix ARC build errors drm/amdgpu: fix NULL pointer dereference for Renoir
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commit
fd330b1bc2
@ -694,12 +694,12 @@ static void soc15_reg_base_init(struct amdgpu_device *adev)
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* it doesn't support SRIOV. */
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if (amdgpu_discovery) {
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r = amdgpu_discovery_reg_base_init(adev);
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if (r) {
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DRM_WARN("failed to init reg base from ip discovery table, "
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"fallback to legacy init method\n");
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vega10_reg_base_init(adev);
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}
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if (r == 0)
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break;
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DRM_WARN("failed to init reg base from ip discovery table, "
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"fallback to legacy init method\n");
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}
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vega10_reg_base_init(adev);
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break;
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case CHIP_VEGA20:
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vega20_reg_base_init(adev);
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@ -1409,7 +1409,7 @@ static int dm_late_init(void *handle)
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if (dmcu)
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ret = dmcu_load_iram(dmcu, params);
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else if (adev->dm.dc->ctx->dmub_srv)
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ret = dmub_init_abm_config(adev->dm.dc->res_pool->abm, params);
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ret = dmub_init_abm_config(adev->dm.dc->res_pool, params);
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if (!ret)
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return -EINVAL;
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@ -657,7 +657,7 @@ void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct dmcu_iram_parame
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params, ram_table, big_endian);
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}
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bool dmub_init_abm_config(struct abm *abm,
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bool dmub_init_abm_config(struct resource_pool *res_pool,
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struct dmcu_iram_parameters params)
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{
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struct iram_table_v_2_2 ram_table;
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@ -665,8 +665,13 @@ bool dmub_init_abm_config(struct abm *abm,
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bool result = false;
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uint32_t i, j = 0;
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if (abm == NULL)
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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if (res_pool->abm == NULL && res_pool->multiple_abms[0] == NULL)
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return false;
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#else
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if (res_pool->abm == NULL)
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return false;
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#endif
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memset(&ram_table, 0, sizeof(ram_table));
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memset(&config, 0, sizeof(config));
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@ -707,8 +712,14 @@ bool dmub_init_abm_config(struct abm *abm,
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config.min_abm_backlight = ram_table.min_abm_backlight;
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result = abm->funcs->init_abm_config(
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abm, (char *)(&config), sizeof(struct abm_config_table));
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#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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if (res_pool->multiple_abms[0]) {
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result = res_pool->multiple_abms[0]->funcs->init_abm_config(
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res_pool->multiple_abms[0], (char *)(&config), sizeof(struct abm_config_table));
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} else
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#endif
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result = res_pool->abm->funcs->init_abm_config(
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res_pool->abm, (char *)(&config), sizeof(struct abm_config_table));
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return result;
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}
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@ -28,6 +28,8 @@
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#include "dc/inc/hw/dmcu.h"
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#include "dc/inc/hw/abm.h"
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struct resource_pool;
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enum abm_defines {
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abm_defines_max_level = 4,
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@ -45,7 +47,7 @@ struct dmcu_iram_parameters {
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bool dmcu_load_iram(struct dmcu *dmcu,
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struct dmcu_iram_parameters params);
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bool dmub_init_abm_config(struct abm *abm,
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bool dmub_init_abm_config(struct resource_pool *res_pool,
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struct dmcu_iram_parameters params);
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#endif /* MODULES_POWER_POWER_HELPERS_H_ */
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@ -2265,8 +2265,6 @@ static void navi10_fill_i2c_req(SwI2cRequest_t *req, bool write,
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{
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int i;
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BUG_ON(numbytes > MAX_SW_I2C_COMMANDS);
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req->I2CcontrollerPort = 0;
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req->I2CSpeed = 2;
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req->SlaveAddress = address;
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@ -2304,6 +2302,12 @@ static int navi10_i2c_read_data(struct i2c_adapter *control,
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struct smu_table_context *smu_table = &adev->smu.smu_table;
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struct smu_table *table = &smu_table->driver_table;
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if (numbytes > MAX_SW_I2C_COMMANDS) {
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dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
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numbytes, MAX_SW_I2C_COMMANDS);
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return -EINVAL;
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}
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memset(&req, 0, sizeof(req));
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navi10_fill_i2c_req(&req, false, address, numbytes, data);
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@ -2340,6 +2344,12 @@ static int navi10_i2c_write_data(struct i2c_adapter *control,
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SwI2cRequest_t req;
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struct amdgpu_device *adev = to_amdgpu_device(control);
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if (numbytes > MAX_SW_I2C_COMMANDS) {
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dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
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numbytes, MAX_SW_I2C_COMMANDS);
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return -EINVAL;
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}
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memset(&req, 0, sizeof(req));
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navi10_fill_i2c_req(&req, true, address, numbytes, data);
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@ -2445,8 +2445,6 @@ static void sienna_cichlid_fill_i2c_req(SwI2cRequest_t *req, bool write,
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{
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int i;
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BUG_ON(numbytes > MAX_SW_I2C_COMMANDS);
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req->I2CcontrollerPort = 0;
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req->I2CSpeed = 2;
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req->SlaveAddress = address;
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@ -2484,6 +2482,12 @@ static int sienna_cichlid_i2c_read_data(struct i2c_adapter *control,
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struct smu_table_context *smu_table = &adev->smu.smu_table;
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struct smu_table *table = &smu_table->driver_table;
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if (numbytes > MAX_SW_I2C_COMMANDS) {
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dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
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numbytes, MAX_SW_I2C_COMMANDS);
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return -EINVAL;
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}
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memset(&req, 0, sizeof(req));
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sienna_cichlid_fill_i2c_req(&req, false, address, numbytes, data);
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@ -2520,6 +2524,12 @@ static int sienna_cichlid_i2c_write_data(struct i2c_adapter *control,
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SwI2cRequest_t req;
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struct amdgpu_device *adev = to_amdgpu_device(control);
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if (numbytes > MAX_SW_I2C_COMMANDS) {
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dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
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numbytes, MAX_SW_I2C_COMMANDS);
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return -EINVAL;
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}
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memset(&req, 0, sizeof(req));
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sienna_cichlid_fill_i2c_req(&req, true, address, numbytes, data);
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