renegade-project/linux-next
2
0
Fork 0
mirror of https://github.com/edk2-porting/linux-next.git synced 2025-01-17 10:04:14 +08:00
Code

staging: rtl8188eu: Fixed "Missing a blank line after declarations".

Browse Source 
Fixed checkpatch.pl "missing a blank line after declarations" waring
messages from rtl8188eu module.

Signed-off-by: Yamanappagouda Patil <goudapatilk@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Yamanappagouda Patil 2017-02-21 20:29:21 +05:30 committed by Greg Kroah-Hartman
parent 2f55aa5483
commit fc988e144c
7 changed files with 22 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/staging/rtl8188eu/hal/odm.c
View File

@ -832,6 +832,7 @@ void odm_RefreshRateAdaptiveMaskCE(struct odm_dm_struct *pDM_Odm)
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i]; struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i];
if (IS_STA_VALID(pstat)) { if (IS_STA_VALID(pstat)) {
if (ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false, &pstat->rssi_level)) { if (ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false, &pstat->rssi_level)) {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
@ -896,6 +897,7 @@ void odm_DynamicTxPowerInit(struct odm_dm_struct *pDM_Odm)
{ {
struct adapter *Adapter = pDM_Odm->Adapter; struct adapter *Adapter = pDM_Odm->Adapter;
struct dm_priv *pdmpriv = &Adapter->HalData->dmpriv; struct dm_priv *pdmpriv = &Adapter->HalData->dmpriv;
pdmpriv->bDynamicTxPowerEnable = false; pdmpriv->bDynamicTxPowerEnable = false;
pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal; pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal;
pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
@ -1052,6 +1054,7 @@ void odm_HwAntDiv(struct odm_dm_struct *pDM_Odm)
void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm) void ODM_EdcaTurboInit(struct odm_dm_struct *pDM_Odm)
{ {
struct adapter *Adapter = pDM_Odm->Adapter; struct adapter *Adapter = pDM_Odm->Adapter;
pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false; pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false; pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
Adapter->recvpriv.bIsAnyNonBEPkts = false; Adapter->recvpriv.bIsAnyNonBEPkts = false;

1
drivers/staging/rtl8188eu/hal/odm_RTL8188E.c
View File

@ -248,6 +248,7 @@ void rtl88eu_dm_ant_sel_statistics(struct odm_dm_struct *dm_odm,
u8 antsel_tr_mux, u32 mac_id, u8 rx_pwdb_all) u8 antsel_tr_mux, u32 mac_id, u8 rx_pwdb_all)
{ {
struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable; struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) { if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
if (antsel_tr_mux == MAIN_ANT_CG_TRX) { if (antsel_tr_mux == MAIN_ANT_CG_TRX) {
dm_fat_tbl->MainAnt_Sum[mac_id] += rx_pwdb_all; dm_fat_tbl->MainAnt_Sum[mac_id] += rx_pwdb_all;

1
drivers/staging/rtl8188eu/hal/phy.c
View File

@ -1005,6 +1005,7 @@ static void phy_iq_calibrate(struct adapter *adapt, s32 result[][8],
rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD}; rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD};
u32 retry_count = 9; u32 retry_count = 9;
if (*(dm_odm->mp_mode) == 1) if (*(dm_odm->mp_mode) == 1)
retry_count = 9; retry_count = 9;
else else

1
drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c
View File

@ -210,6 +210,7 @@ void rtl8188e_set_FwMediaStatus_cmd(struct adapter *adapt, __le16 mstatus_rpt)
{ {
u8 opmode, macid; u8 opmode, macid;
u16 mst_rpt = le16_to_cpu(mstatus_rpt); u16 mst_rpt = le16_to_cpu(mstatus_rpt);
opmode = (u8)mst_rpt; opmode = (u8)mst_rpt;
macid = (u8)(mst_rpt >> 8); macid = (u8)(mst_rpt >> 8);

1
drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c
View File

@ -70,6 +70,7 @@ s32 iol_execute(struct adapter *padapter, u8 control)
static s32 iol_InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy) static s32 iol_InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy)
{ {
s32 rst = _SUCCESS; s32 rst = _SUCCESS;
iol_mode_enable(padapter, 1); iol_mode_enable(padapter, 1);
usb_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy); usb_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy);
rst = iol_execute(padapter, CMD_INIT_LLT); rst = iol_execute(padapter, CMD_INIT_LLT);

1
drivers/staging/rtl8188eu/hal/rtl8188eu_xmit.c
View File

@ -347,6 +347,7 @@ static s32 rtw_dump_xframe(struct adapter *adapt, struct xmit_frame *pxmitframe)
struct pkt_attrib *pattrib = &pxmitframe->attrib; struct pkt_attrib *pattrib = &pxmitframe->attrib;
struct xmit_priv *pxmitpriv = &adapt->xmitpriv; struct xmit_priv *pxmitpriv = &adapt->xmitpriv;
struct security_priv *psecuritypriv = &adapt->securitypriv; struct security_priv *psecuritypriv = &adapt->securitypriv;
if ((pxmitframe->frame_tag == DATA_FRAMETAG) && if ((pxmitframe->frame_tag == DATA_FRAMETAG) &&
(pxmitframe->attrib.ether_type != 0x0806) && (pxmitframe->attrib.ether_type != 0x0806) &&
(pxmitframe->attrib.ether_type != 0x888e) && (pxmitframe->attrib.ether_type != 0x888e) &&

14
drivers/staging/rtl8188eu/hal/usb_halinit.c
View File

@ -337,6 +337,7 @@ static void _InitTransferPageSize(struct adapter *Adapter)
/* Tx page size is always 128. */ /* Tx page size is always 128. */
u8 value8; u8 value8;
value8 = _PSRX(PBP_128) | _PSTX(PBP_128); value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
usb_write8(Adapter, REG_PBP, value8); usb_write8(Adapter, REG_PBP, value8);
} }
@ -1361,6 +1362,7 @@ void rtw_hal_set_hwreg(struct adapter *Adapter, u8 variable, u8 *val)
if (*((u8 *)val)) { /* under sitesurvey */ if (*((u8 *)val)) { /* under sitesurvey */
/* config RCR to receive different BSSID & not to receive data frame */ /* config RCR to receive different BSSID & not to receive data frame */
u32 v = usb_read32(Adapter, REG_RCR); u32 v = usb_read32(Adapter, REG_RCR);
v &= ~(RCR_CBSSID_BCN); v &= ~(RCR_CBSSID_BCN);
usb_write32(Adapter, REG_RCR, v); usb_write32(Adapter, REG_RCR, v);
/* reject all data frame */ /* reject all data frame */
@ -1514,6 +1516,7 @@ void rtw_hal_set_hwreg(struct adapter *Adapter, u8 variable, u8 *val)
case HW_VAR_CAM_WRITE: case HW_VAR_CAM_WRITE:
{ {
u32 cmd; u32 cmd;
u32 *cam_val = (u32 *)val; u32 *cam_val = (u32 *)val;
usb_write32(Adapter, WCAMI, cam_val[0]); usb_write32(Adapter, WCAMI, cam_val[0]);
@ -1618,6 +1621,7 @@ void rtw_hal_set_hwreg(struct adapter *Adapter, u8 variable, u8 *val)
case HW_VAR_RXDMA_AGG_PG_TH: case HW_VAR_RXDMA_AGG_PG_TH:
{ {
u8 threshold = *((u8 *)val); u8 threshold = *((u8 *)val);
if (threshold == 0) if (threshold == 0)
threshold = haldata->UsbRxAggPageCount; threshold = haldata->UsbRxAggPageCount;
usb_write8(Adapter, REG_RXDMA_AGG_PG_TH, threshold); usb_write8(Adapter, REG_RXDMA_AGG_PG_TH, threshold);
@ -1639,6 +1643,7 @@ void rtw_hal_set_hwreg(struct adapter *Adapter, u8 variable, u8 *val)
case HW_VAR_H2C_FW_JOINBSSRPT: case HW_VAR_H2C_FW_JOINBSSRPT:
{ {
u8 mstatus = (*(u8 *)val); u8 mstatus = (*(u8 *)val);
rtl8188e_set_FwJoinBssReport_cmd(Adapter, mstatus); rtl8188e_set_FwJoinBssReport_cmd(Adapter, mstatus);
} }
break; break;
@ -1661,6 +1666,7 @@ void rtw_hal_set_hwreg(struct adapter *Adapter, u8 variable, u8 *val)
case HW_VAR_RPT_TIMER_SETTING: case HW_VAR_RPT_TIMER_SETTING:
{ {
u16 min_rpt_time = (*(u16 *)val); u16 min_rpt_time = (*(u16 *)val);
ODM_RA_Set_TxRPT_Time(podmpriv, min_rpt_time); ODM_RA_Set_TxRPT_Time(podmpriv, min_rpt_time);
} }
break; break;
@ -1717,6 +1723,7 @@ void rtw_hal_set_hwreg(struct adapter *Adapter, u8 variable, u8 *val)
case HW_VAR_TX_RPT_MAX_MACID: case HW_VAR_TX_RPT_MAX_MACID:
{ {
u8 maxMacid = *val; u8 maxMacid = *val;
DBG_88E("### MacID(%d),Set Max Tx RPT MID(%d)\n", maxMacid, maxMacid+1); DBG_88E("### MacID(%d),Set Max Tx RPT MID(%d)\n", maxMacid, maxMacid+1);
usb_write8(Adapter, REG_TX_RPT_CTRL+1, maxMacid+1); usb_write8(Adapter, REG_TX_RPT_CTRL+1, maxMacid+1);
} }
@ -1754,6 +1761,7 @@ void rtw_hal_get_hwreg(struct adapter *Adapter, u8 variable, u8 *val)
val[0] = true; val[0] = true;
} else { } else {
u32 valRCR; u32 valRCR;
valRCR = usb_read32(Adapter, REG_RCR); valRCR = usb_read32(Adapter, REG_RCR);
valRCR &= 0x00070000; valRCR &= 0x00070000;
if (valRCR) if (valRCR)
@ -1799,6 +1807,7 @@ u8 rtw_hal_get_def_var(
struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
struct sta_priv *pstapriv = &Adapter->stapriv; struct sta_priv *pstapriv = &Adapter->stapriv;
struct sta_info *psta; struct sta_info *psta;
psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress); psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
if (psta) if (psta)
*((int *)pValue) = psta->rssi_stat.UndecoratedSmoothedPWDB; *((int *)pValue) = psta->rssi_stat.UndecoratedSmoothedPWDB;
@ -1825,18 +1834,21 @@ u8 rtw_hal_get_def_var(
case HAL_DEF_RA_DECISION_RATE: case HAL_DEF_RA_DECISION_RATE:
{ {
u8 MacID = *((u8 *)pValue); u8 MacID = *((u8 *)pValue);
*((u8 *)pValue) = ODM_RA_GetDecisionRate_8188E(&haldata->odmpriv, MacID); *((u8 *)pValue) = ODM_RA_GetDecisionRate_8188E(&haldata->odmpriv, MacID);
} }
break; break;
case HAL_DEF_RA_SGI: case HAL_DEF_RA_SGI:
{ {
u8 MacID = *((u8 *)pValue); u8 MacID = *((u8 *)pValue);
*((u8 *)pValue) = ODM_RA_GetShortGI_8188E(&haldata->odmpriv, MacID); *((u8 *)pValue) = ODM_RA_GetShortGI_8188E(&haldata->odmpriv, MacID);
} }
break; break;
case HAL_DEF_PT_PWR_STATUS: case HAL_DEF_PT_PWR_STATUS:
{ {
u8 MacID = *((u8 *)pValue); u8 MacID = *((u8 *)pValue);
*((u8 *)pValue) = ODM_RA_GetHwPwrStatus_8188E(&haldata->odmpriv, MacID); *((u8 *)pValue) = ODM_RA_GetHwPwrStatus_8188E(&haldata->odmpriv, MacID);
} }
break; break;
@ -1846,6 +1858,7 @@ u8 rtw_hal_get_def_var(
case HW_DEF_RA_INFO_DUMP: case HW_DEF_RA_INFO_DUMP:
{ {
u8 entry_id = *((u8 *)pValue); u8 entry_id = *((u8 *)pValue);
if (check_fwstate(&Adapter->mlmepriv, _FW_LINKED)) { if (check_fwstate(&Adapter->mlmepriv, _FW_LINKED)) {
DBG_88E("============ RA status check ===================\n"); DBG_88E("============ RA status check ===================\n");
DBG_88E("Mac_id:%d , RateID = %d, RAUseRate = 0x%08x, RateSGI = %d, DecisionRate = 0x%02x ,PTStage = %d\n", DBG_88E("Mac_id:%d , RateID = %d, RAUseRate = 0x%08x, RateSGI = %d, DecisionRate = 0x%02x ,PTStage = %d\n",
@ -1861,6 +1874,7 @@ u8 rtw_hal_get_def_var(
case HW_DEF_ODM_DBG_FLAG: case HW_DEF_ODM_DBG_FLAG:
{ {
struct odm_dm_struct *dm_ocm = &haldata->odmpriv; struct odm_dm_struct *dm_ocm = &haldata->odmpriv;
pr_info("dm_ocm->DebugComponents = 0x%llx\n", dm_ocm->DebugComponents); pr_info("dm_ocm->DebugComponents = 0x%llx\n", dm_ocm->DebugComponents);
} }
break; break;