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mirror of https://github.com/edk2-porting/linux-next.git synced 2024-12-27 06:34:11 +08:00

ionic: Add hardware init and device commands

The ionic device has a small set of PCI registers, including a
device control and data space, and a large set of message
commands.

Also adds new DEVLINK_INFO_VERSION_GENERIC tags for
ASIC_ID, ASIC_REV, and FW.

Signed-off-by: Shannon Nelson <snelson@pensando.io>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Shannon Nelson 2019-09-03 15:28:05 -07:00 committed by David S. Miller
parent df69ba4321
commit fbfb803153
13 changed files with 3481 additions and 2 deletions

View File

@ -3,4 +3,5 @@
obj-$(CONFIG_IONIC) := ionic.o
ionic-y := ionic_main.o ionic_bus_pci.o ionic_devlink.o
ionic-y := ionic_main.o ionic_bus_pci.o ionic_devlink.o ionic_dev.o \
ionic_debugfs.o

View File

@ -4,6 +4,8 @@
#ifndef _IONIC_H_
#define _IONIC_H_
#include "ionic_if.h"
#include "ionic_dev.h"
#include "ionic_devlink.h"
#define IONIC_DRV_NAME "ionic"
@ -19,9 +21,25 @@
#define IONIC_SUBDEV_ID_NAPLES_100_4 0x4001
#define IONIC_SUBDEV_ID_NAPLES_100_8 0x4002
#define DEVCMD_TIMEOUT 10
struct ionic {
struct pci_dev *pdev;
struct device *dev;
struct ionic_dev idev;
struct mutex dev_cmd_lock; /* lock for dev_cmd operations */
struct dentry *dentry;
struct ionic_dev_bar bars[IONIC_BARS_MAX];
unsigned int num_bars;
struct ionic_identity ident;
};
int ionic_dev_cmd_wait(struct ionic *ionic, unsigned long max_wait);
int ionic_set_dma_mask(struct ionic *ionic);
int ionic_setup(struct ionic *ionic);
int ionic_identify(struct ionic *ionic);
int ionic_init(struct ionic *ionic);
int ionic_reset(struct ionic *ionic);
#endif /* _IONIC_H_ */

View File

@ -4,6 +4,7 @@
#ifndef _IONIC_BUS_H_
#define _IONIC_BUS_H_
const char *ionic_bus_info(struct ionic *ionic);
int ionic_bus_register_driver(void);
void ionic_bus_unregister_driver(void);

View File

@ -8,6 +8,7 @@
#include "ionic.h"
#include "ionic_bus.h"
#include "ionic_debugfs.h"
/* Supported devices */
static const struct pci_device_id ionic_id_table[] = {
@ -17,10 +18,68 @@ static const struct pci_device_id ionic_id_table[] = {
};
MODULE_DEVICE_TABLE(pci, ionic_id_table);
const char *ionic_bus_info(struct ionic *ionic)
{
return pci_name(ionic->pdev);
}
static int ionic_map_bars(struct ionic *ionic)
{
struct pci_dev *pdev = ionic->pdev;
struct device *dev = ionic->dev;
struct ionic_dev_bar *bars;
unsigned int i, j;
bars = ionic->bars;
ionic->num_bars = 0;
for (i = 0, j = 0; i < IONIC_BARS_MAX; i++) {
if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM))
continue;
bars[j].len = pci_resource_len(pdev, i);
/* only map the whole bar 0 */
if (j > 0) {
bars[j].vaddr = NULL;
} else {
bars[j].vaddr = pci_iomap(pdev, i, bars[j].len);
if (!bars[j].vaddr) {
dev_err(dev,
"Cannot memory-map BAR %d, aborting\n",
i);
return -ENODEV;
}
}
bars[j].bus_addr = pci_resource_start(pdev, i);
bars[j].res_index = i;
ionic->num_bars++;
j++;
}
return 0;
}
static void ionic_unmap_bars(struct ionic *ionic)
{
struct ionic_dev_bar *bars = ionic->bars;
unsigned int i;
for (i = 0; i < IONIC_BARS_MAX; i++) {
if (bars[i].vaddr) {
iounmap(bars[i].vaddr);
bars[i].bus_addr = 0;
bars[i].vaddr = NULL;
bars[i].len = 0;
}
}
}
static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
struct device *dev = &pdev->dev;
struct ionic *ionic;
int err;
ionic = ionic_devlink_alloc(dev);
if (!ionic)
@ -29,14 +88,96 @@ static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
ionic->pdev = pdev;
ionic->dev = dev;
pci_set_drvdata(pdev, ionic);
mutex_init(&ionic->dev_cmd_lock);
/* Query system for DMA addressing limitation for the device. */
err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(IONIC_ADDR_LEN));
if (err) {
dev_err(dev, "Unable to obtain 64-bit DMA for consistent allocations, aborting. err=%d\n",
err);
goto err_out_clear_drvdata;
}
ionic_debugfs_add_dev(ionic);
/* Setup PCI device */
err = pci_enable_device_mem(pdev);
if (err) {
dev_err(dev, "Cannot enable PCI device: %d, aborting\n", err);
goto err_out_debugfs_del_dev;
}
err = pci_request_regions(pdev, IONIC_DRV_NAME);
if (err) {
dev_err(dev, "Cannot request PCI regions: %d, aborting\n", err);
goto err_out_pci_disable_device;
}
pci_set_master(pdev);
err = ionic_map_bars(ionic);
if (err)
goto err_out_pci_clear_master;
/* Configure the device */
err = ionic_setup(ionic);
if (err) {
dev_err(dev, "Cannot setup device: %d, aborting\n", err);
goto err_out_unmap_bars;
}
err = ionic_identify(ionic);
if (err) {
dev_err(dev, "Cannot identify device: %d, aborting\n", err);
goto err_out_teardown;
}
err = ionic_init(ionic);
if (err) {
dev_err(dev, "Cannot init device: %d, aborting\n", err);
goto err_out_teardown;
}
err = ionic_devlink_register(ionic);
if (err)
dev_err(dev, "Cannot register devlink: %d\n", err);
return 0;
err_out_teardown:
ionic_dev_teardown(ionic);
err_out_unmap_bars:
ionic_unmap_bars(ionic);
pci_release_regions(pdev);
err_out_pci_clear_master:
pci_clear_master(pdev);
err_out_pci_disable_device:
pci_disable_device(pdev);
err_out_debugfs_del_dev:
ionic_debugfs_del_dev(ionic);
err_out_clear_drvdata:
mutex_destroy(&ionic->dev_cmd_lock);
ionic_devlink_free(ionic);
return err;
}
static void ionic_remove(struct pci_dev *pdev)
{
struct ionic *ionic = pci_get_drvdata(pdev);
if (!ionic)
return;
ionic_devlink_unregister(ionic);
ionic_reset(ionic);
ionic_dev_teardown(ionic);
ionic_unmap_bars(ionic);
pci_release_regions(pdev);
pci_clear_master(pdev);
pci_disable_device(pdev);
ionic_debugfs_del_dev(ionic);
mutex_destroy(&ionic->dev_cmd_lock);
ionic_devlink_free(ionic);
}

View File

@ -0,0 +1,61 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
#include <linux/netdevice.h>
#include "ionic.h"
#include "ionic_bus.h"
#include "ionic_debugfs.h"
#ifdef CONFIG_DEBUG_FS
static struct dentry *ionic_dir;
void ionic_debugfs_create(void)
{
ionic_dir = debugfs_create_dir(IONIC_DRV_NAME, NULL);
}
void ionic_debugfs_destroy(void)
{
debugfs_remove_recursive(ionic_dir);
}
void ionic_debugfs_add_dev(struct ionic *ionic)
{
ionic->dentry = debugfs_create_dir(ionic_bus_info(ionic), ionic_dir);
}
void ionic_debugfs_del_dev(struct ionic *ionic)
{
debugfs_remove_recursive(ionic->dentry);
ionic->dentry = NULL;
}
static int identity_show(struct seq_file *seq, void *v)
{
struct ionic *ionic = seq->private;
struct ionic_identity *ident;
ident = &ionic->ident;
seq_printf(seq, "nlifs: %d\n", ident->dev.nlifs);
seq_printf(seq, "nintrs: %d\n", ident->dev.nintrs);
seq_printf(seq, "ndbpgs_per_lif: %d\n", ident->dev.ndbpgs_per_lif);
seq_printf(seq, "intr_coal_mult: %d\n", ident->dev.intr_coal_mult);
seq_printf(seq, "intr_coal_div: %d\n", ident->dev.intr_coal_div);
seq_printf(seq, "max_ucast_filters: %d\n", ident->lif.eth.max_ucast_filters);
seq_printf(seq, "max_mcast_filters: %d\n", ident->lif.eth.max_mcast_filters);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(identity);
void ionic_debugfs_add_ident(struct ionic *ionic)
{
debugfs_create_file("identity", 0400, ionic->dentry,
ionic, &identity_fops) ? 0 : -EOPNOTSUPP;
}
#endif

View File

@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
#ifndef _IONIC_DEBUGFS_H_
#define _IONIC_DEBUGFS_H_
#include <linux/debugfs.h>
#ifdef CONFIG_DEBUG_FS
void ionic_debugfs_create(void);
void ionic_debugfs_destroy(void);
void ionic_debugfs_add_dev(struct ionic *ionic);
void ionic_debugfs_del_dev(struct ionic *ionic);
void ionic_debugfs_add_ident(struct ionic *ionic);
#else
static inline void ionic_debugfs_create(void) { }
static inline void ionic_debugfs_destroy(void) { }
static inline void ionic_debugfs_add_dev(struct ionic *ionic) { }
static inline void ionic_debugfs_del_dev(struct ionic *ionic) { }
static inline void ionic_debugfs_add_ident(struct ionic *ionic) { }
#endif
#endif /* _IONIC_DEBUGFS_H_ */

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@ -0,0 +1,136 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/etherdevice.h>
#include "ionic.h"
#include "ionic_dev.h"
void ionic_init_devinfo(struct ionic *ionic)
{
struct ionic_dev *idev = &ionic->idev;
idev->dev_info.asic_type = ioread8(&idev->dev_info_regs->asic_type);
idev->dev_info.asic_rev = ioread8(&idev->dev_info_regs->asic_rev);
memcpy_fromio(idev->dev_info.fw_version,
idev->dev_info_regs->fw_version,
IONIC_DEVINFO_FWVERS_BUFLEN);
memcpy_fromio(idev->dev_info.serial_num,
idev->dev_info_regs->serial_num,
IONIC_DEVINFO_SERIAL_BUFLEN);
idev->dev_info.fw_version[IONIC_DEVINFO_FWVERS_BUFLEN] = 0;
idev->dev_info.serial_num[IONIC_DEVINFO_SERIAL_BUFLEN] = 0;
dev_dbg(ionic->dev, "fw_version %s\n", idev->dev_info.fw_version);
}
int ionic_dev_setup(struct ionic *ionic)
{
struct ionic_dev_bar *bar = ionic->bars;
unsigned int num_bars = ionic->num_bars;
struct ionic_dev *idev = &ionic->idev;
struct device *dev = ionic->dev;
u32 sig;
/* BAR0: dev_cmd and interrupts */
if (num_bars < 1) {
dev_err(dev, "No bars found, aborting\n");
return -EFAULT;
}
if (bar->len < IONIC_BAR0_SIZE) {
dev_err(dev, "Resource bar size %lu too small, aborting\n",
bar->len);
return -EFAULT;
}
idev->dev_info_regs = bar->vaddr + IONIC_BAR0_DEV_INFO_REGS_OFFSET;
idev->dev_cmd_regs = bar->vaddr + IONIC_BAR0_DEV_CMD_REGS_OFFSET;
idev->intr_status = bar->vaddr + IONIC_BAR0_INTR_STATUS_OFFSET;
idev->intr_ctrl = bar->vaddr + IONIC_BAR0_INTR_CTRL_OFFSET;
sig = ioread32(&idev->dev_info_regs->signature);
if (sig != IONIC_DEV_INFO_SIGNATURE) {
dev_err(dev, "Incompatible firmware signature %x", sig);
return -EFAULT;
}
ionic_init_devinfo(ionic);
/* BAR1: doorbells */
bar++;
if (num_bars < 2) {
dev_err(dev, "Doorbell bar missing, aborting\n");
return -EFAULT;
}
idev->db_pages = bar->vaddr;
idev->phy_db_pages = bar->bus_addr;
return 0;
}
void ionic_dev_teardown(struct ionic *ionic)
{
/* place holder */
}
/* Devcmd Interface */
u8 ionic_dev_cmd_status(struct ionic_dev *idev)
{
return ioread8(&idev->dev_cmd_regs->comp.comp.status);
}
bool ionic_dev_cmd_done(struct ionic_dev *idev)
{
return ioread32(&idev->dev_cmd_regs->done) & IONIC_DEV_CMD_DONE;
}
void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp)
{
memcpy_fromio(comp, &idev->dev_cmd_regs->comp, sizeof(*comp));
}
void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd)
{
memcpy_toio(&idev->dev_cmd_regs->cmd, cmd, sizeof(*cmd));
iowrite32(0, &idev->dev_cmd_regs->done);
iowrite32(1, &idev->dev_cmd_regs->doorbell);
}
/* Device commands */
void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver)
{
union ionic_dev_cmd cmd = {
.identify.opcode = IONIC_CMD_IDENTIFY,
.identify.ver = ver,
};
ionic_dev_cmd_go(idev, &cmd);
}
void ionic_dev_cmd_init(struct ionic_dev *idev)
{
union ionic_dev_cmd cmd = {
.init.opcode = IONIC_CMD_INIT,
.init.type = 0,
};
ionic_dev_cmd_go(idev, &cmd);
}
void ionic_dev_cmd_reset(struct ionic_dev *idev)
{
union ionic_dev_cmd cmd = {
.reset.opcode = IONIC_CMD_RESET,
};
ionic_dev_cmd_go(idev, &cmd);
}

View File

@ -0,0 +1,138 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
#ifndef _IONIC_DEV_H_
#define _IONIC_DEV_H_
#include <linux/mutex.h>
#include <linux/workqueue.h>
#include "ionic_if.h"
#include "ionic_regs.h"
struct ionic_dev_bar {
void __iomem *vaddr;
phys_addr_t bus_addr;
unsigned long len;
int res_index;
};
/* Registers */
static_assert(sizeof(struct ionic_intr) == 32);
static_assert(sizeof(struct ionic_doorbell) == 8);
static_assert(sizeof(struct ionic_intr_status) == 8);
static_assert(sizeof(union ionic_dev_regs) == 4096);
static_assert(sizeof(union ionic_dev_info_regs) == 2048);
static_assert(sizeof(union ionic_dev_cmd_regs) == 2048);
static_assert(sizeof(struct ionic_lif_stats) == 1024);
static_assert(sizeof(struct ionic_admin_cmd) == 64);
static_assert(sizeof(struct ionic_admin_comp) == 16);
static_assert(sizeof(struct ionic_nop_cmd) == 64);
static_assert(sizeof(struct ionic_nop_comp) == 16);
/* Device commands */
static_assert(sizeof(struct ionic_dev_identify_cmd) == 64);
static_assert(sizeof(struct ionic_dev_identify_comp) == 16);
static_assert(sizeof(struct ionic_dev_init_cmd) == 64);
static_assert(sizeof(struct ionic_dev_init_comp) == 16);
static_assert(sizeof(struct ionic_dev_reset_cmd) == 64);
static_assert(sizeof(struct ionic_dev_reset_comp) == 16);
static_assert(sizeof(struct ionic_dev_getattr_cmd) == 64);
static_assert(sizeof(struct ionic_dev_getattr_comp) == 16);
static_assert(sizeof(struct ionic_dev_setattr_cmd) == 64);
static_assert(sizeof(struct ionic_dev_setattr_comp) == 16);
/* Port commands */
static_assert(sizeof(struct ionic_port_identify_cmd) == 64);
static_assert(sizeof(struct ionic_port_identify_comp) == 16);
static_assert(sizeof(struct ionic_port_init_cmd) == 64);
static_assert(sizeof(struct ionic_port_init_comp) == 16);
static_assert(sizeof(struct ionic_port_reset_cmd) == 64);
static_assert(sizeof(struct ionic_port_reset_comp) == 16);
static_assert(sizeof(struct ionic_port_getattr_cmd) == 64);
static_assert(sizeof(struct ionic_port_getattr_comp) == 16);
static_assert(sizeof(struct ionic_port_setattr_cmd) == 64);
static_assert(sizeof(struct ionic_port_setattr_comp) == 16);
/* LIF commands */
static_assert(sizeof(struct ionic_lif_init_cmd) == 64);
static_assert(sizeof(struct ionic_lif_init_comp) == 16);
static_assert(sizeof(struct ionic_lif_reset_cmd) == 64);
static_assert(sizeof(ionic_lif_reset_comp) == 16);
static_assert(sizeof(struct ionic_lif_getattr_cmd) == 64);
static_assert(sizeof(struct ionic_lif_getattr_comp) == 16);
static_assert(sizeof(struct ionic_lif_setattr_cmd) == 64);
static_assert(sizeof(struct ionic_lif_setattr_comp) == 16);
static_assert(sizeof(struct ionic_q_init_cmd) == 64);
static_assert(sizeof(struct ionic_q_init_comp) == 16);
static_assert(sizeof(struct ionic_q_control_cmd) == 64);
static_assert(sizeof(ionic_q_control_comp) == 16);
static_assert(sizeof(struct ionic_rx_mode_set_cmd) == 64);
static_assert(sizeof(ionic_rx_mode_set_comp) == 16);
static_assert(sizeof(struct ionic_rx_filter_add_cmd) == 64);
static_assert(sizeof(struct ionic_rx_filter_add_comp) == 16);
static_assert(sizeof(struct ionic_rx_filter_del_cmd) == 64);
static_assert(sizeof(ionic_rx_filter_del_comp) == 16);
/* RDMA commands */
static_assert(sizeof(struct ionic_rdma_reset_cmd) == 64);
static_assert(sizeof(struct ionic_rdma_queue_cmd) == 64);
/* Events */
static_assert(sizeof(struct ionic_notifyq_cmd) == 4);
static_assert(sizeof(union ionic_notifyq_comp) == 64);
static_assert(sizeof(struct ionic_notifyq_event) == 64);
static_assert(sizeof(struct ionic_link_change_event) == 64);
static_assert(sizeof(struct ionic_reset_event) == 64);
static_assert(sizeof(struct ionic_heartbeat_event) == 64);
static_assert(sizeof(struct ionic_log_event) == 64);
/* I/O */
static_assert(sizeof(struct ionic_txq_desc) == 16);
static_assert(sizeof(struct ionic_txq_sg_desc) == 128);
static_assert(sizeof(struct ionic_txq_comp) == 16);
static_assert(sizeof(struct ionic_rxq_desc) == 16);
static_assert(sizeof(struct ionic_rxq_sg_desc) == 128);
static_assert(sizeof(struct ionic_rxq_comp) == 16);
struct ionic_devinfo {
u8 asic_type;
u8 asic_rev;
char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN + 1];
char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN + 1];
};
struct ionic_dev {
union ionic_dev_info_regs __iomem *dev_info_regs;
union ionic_dev_cmd_regs __iomem *dev_cmd_regs;
u64 __iomem *db_pages;
dma_addr_t phy_db_pages;
struct ionic_intr __iomem *intr_ctrl;
u64 __iomem *intr_status;
struct ionic_devinfo dev_info;
};
struct ionic;
void ionic_init_devinfo(struct ionic *ionic);
int ionic_dev_setup(struct ionic *ionic);
void ionic_dev_teardown(struct ionic *ionic);
void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd);
u8 ionic_dev_cmd_status(struct ionic_dev *idev);
bool ionic_dev_cmd_done(struct ionic_dev *idev);
void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp);
void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver);
void ionic_dev_cmd_init(struct ionic_dev *idev);
void ionic_dev_cmd_reset(struct ionic_dev *idev);
#endif /* _IONIC_DEV_H_ */

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@ -11,7 +11,39 @@
static int ionic_dl_info_get(struct devlink *dl, struct devlink_info_req *req,
struct netlink_ext_ack *extack)
{
return devlink_info_driver_name_put(req, IONIC_DRV_NAME);
struct ionic *ionic = devlink_priv(dl);
struct ionic_dev *idev = &ionic->idev;
char buf[16];
int err = 0;
err = devlink_info_driver_name_put(req, IONIC_DRV_NAME);
if (err)
goto info_out;
err = devlink_info_version_running_put(req,
DEVLINK_INFO_VERSION_GENERIC_FW,
idev->dev_info.fw_version);
if (err)
goto info_out;
snprintf(buf, sizeof(buf), "0x%x", idev->dev_info.asic_type);
err = devlink_info_version_fixed_put(req,
DEVLINK_INFO_VERSION_GENERIC_ASIC_ID,
buf);
if (err)
goto info_out;
snprintf(buf, sizeof(buf), "0x%x", idev->dev_info.asic_rev);
err = devlink_info_version_fixed_put(req,
DEVLINK_INFO_VERSION_GENERIC_ASIC_REV,
buf);
if (err)
goto info_out;
err = devlink_info_serial_number_put(req, idev->dev_info.serial_num);
info_out:
return err;
}
static const struct devlink_ops ionic_dl_ops = {
@ -33,3 +65,22 @@ void ionic_devlink_free(struct ionic *ionic)
devlink_free(dl);
}
int ionic_devlink_register(struct ionic *ionic)
{
struct devlink *dl = priv_to_devlink(ionic);
int err;
err = devlink_register(dl, ionic->dev);
if (err)
dev_warn(ionic->dev, "devlink_register failed: %d\n", err);
return err;
}
void ionic_devlink_unregister(struct ionic *ionic)
{
struct devlink *dl = priv_to_devlink(ionic);
devlink_unregister(dl);
}

View File

@ -8,5 +8,7 @@
struct ionic *ionic_devlink_alloc(struct device *dev);
void ionic_devlink_free(struct ionic *ionic);
int ionic_devlink_register(struct ionic *ionic);
void ionic_devlink_unregister(struct ionic *ionic);
#endif /* _IONIC_DEVLINK_H_ */

File diff suppressed because it is too large Load Diff

View File

@ -8,22 +8,313 @@
#include "ionic.h"
#include "ionic_bus.h"
#include "ionic_debugfs.h"
MODULE_DESCRIPTION(IONIC_DRV_DESCRIPTION);
MODULE_AUTHOR("Pensando Systems, Inc");
MODULE_LICENSE("GPL");
MODULE_VERSION(IONIC_DRV_VERSION);
static const char *ionic_error_to_str(enum ionic_status_code code)
{
switch (code) {
case IONIC_RC_SUCCESS:
return "IONIC_RC_SUCCESS";
case IONIC_RC_EVERSION:
return "IONIC_RC_EVERSION";
case IONIC_RC_EOPCODE:
return "IONIC_RC_EOPCODE";
case IONIC_RC_EIO:
return "IONIC_RC_EIO";
case IONIC_RC_EPERM:
return "IONIC_RC_EPERM";
case IONIC_RC_EQID:
return "IONIC_RC_EQID";
case IONIC_RC_EQTYPE:
return "IONIC_RC_EQTYPE";
case IONIC_RC_ENOENT:
return "IONIC_RC_ENOENT";
case IONIC_RC_EINTR:
return "IONIC_RC_EINTR";
case IONIC_RC_EAGAIN:
return "IONIC_RC_EAGAIN";
case IONIC_RC_ENOMEM:
return "IONIC_RC_ENOMEM";
case IONIC_RC_EFAULT:
return "IONIC_RC_EFAULT";
case IONIC_RC_EBUSY:
return "IONIC_RC_EBUSY";
case IONIC_RC_EEXIST:
return "IONIC_RC_EEXIST";
case IONIC_RC_EINVAL:
return "IONIC_RC_EINVAL";
case IONIC_RC_ENOSPC:
return "IONIC_RC_ENOSPC";
case IONIC_RC_ERANGE:
return "IONIC_RC_ERANGE";
case IONIC_RC_BAD_ADDR:
return "IONIC_RC_BAD_ADDR";
case IONIC_RC_DEV_CMD:
return "IONIC_RC_DEV_CMD";
case IONIC_RC_ERROR:
return "IONIC_RC_ERROR";
case IONIC_RC_ERDMA:
return "IONIC_RC_ERDMA";
default:
return "IONIC_RC_UNKNOWN";
}
}
static int ionic_error_to_errno(enum ionic_status_code code)
{
switch (code) {
case IONIC_RC_SUCCESS:
return 0;
case IONIC_RC_EVERSION:
case IONIC_RC_EQTYPE:
case IONIC_RC_EQID:
case IONIC_RC_EINVAL:
return -EINVAL;
case IONIC_RC_EPERM:
return -EPERM;
case IONIC_RC_ENOENT:
return -ENOENT;
case IONIC_RC_EAGAIN:
return -EAGAIN;
case IONIC_RC_ENOMEM:
return -ENOMEM;
case IONIC_RC_EFAULT:
return -EFAULT;
case IONIC_RC_EBUSY:
return -EBUSY;
case IONIC_RC_EEXIST:
return -EEXIST;
case IONIC_RC_ENOSPC:
return -ENOSPC;
case IONIC_RC_ERANGE:
return -ERANGE;
case IONIC_RC_BAD_ADDR:
return -EFAULT;
case IONIC_RC_EOPCODE:
case IONIC_RC_EINTR:
case IONIC_RC_DEV_CMD:
case IONIC_RC_ERROR:
case IONIC_RC_ERDMA:
case IONIC_RC_EIO:
default:
return -EIO;
}
}
static const char *ionic_opcode_to_str(enum ionic_cmd_opcode opcode)
{
switch (opcode) {
case IONIC_CMD_NOP:
return "IONIC_CMD_NOP";
case IONIC_CMD_INIT:
return "IONIC_CMD_INIT";
case IONIC_CMD_RESET:
return "IONIC_CMD_RESET";
case IONIC_CMD_IDENTIFY:
return "IONIC_CMD_IDENTIFY";
case IONIC_CMD_GETATTR:
return "IONIC_CMD_GETATTR";
case IONIC_CMD_SETATTR:
return "IONIC_CMD_SETATTR";
case IONIC_CMD_PORT_IDENTIFY:
return "IONIC_CMD_PORT_IDENTIFY";
case IONIC_CMD_PORT_INIT:
return "IONIC_CMD_PORT_INIT";
case IONIC_CMD_PORT_RESET:
return "IONIC_CMD_PORT_RESET";
case IONIC_CMD_PORT_GETATTR:
return "IONIC_CMD_PORT_GETATTR";
case IONIC_CMD_PORT_SETATTR:
return "IONIC_CMD_PORT_SETATTR";
case IONIC_CMD_LIF_INIT:
return "IONIC_CMD_LIF_INIT";
case IONIC_CMD_LIF_RESET:
return "IONIC_CMD_LIF_RESET";
case IONIC_CMD_LIF_IDENTIFY:
return "IONIC_CMD_LIF_IDENTIFY";
case IONIC_CMD_LIF_SETATTR:
return "IONIC_CMD_LIF_SETATTR";
case IONIC_CMD_LIF_GETATTR:
return "IONIC_CMD_LIF_GETATTR";
case IONIC_CMD_RX_MODE_SET:
return "IONIC_CMD_RX_MODE_SET";
case IONIC_CMD_RX_FILTER_ADD:
return "IONIC_CMD_RX_FILTER_ADD";
case IONIC_CMD_RX_FILTER_DEL:
return "IONIC_CMD_RX_FILTER_DEL";
case IONIC_CMD_Q_INIT:
return "IONIC_CMD_Q_INIT";
case IONIC_CMD_Q_CONTROL:
return "IONIC_CMD_Q_CONTROL";
case IONIC_CMD_RDMA_RESET_LIF:
return "IONIC_CMD_RDMA_RESET_LIF";
case IONIC_CMD_RDMA_CREATE_EQ:
return "IONIC_CMD_RDMA_CREATE_EQ";
case IONIC_CMD_RDMA_CREATE_CQ:
return "IONIC_CMD_RDMA_CREATE_CQ";
case IONIC_CMD_RDMA_CREATE_ADMINQ:
return "IONIC_CMD_RDMA_CREATE_ADMINQ";
case IONIC_CMD_FW_DOWNLOAD:
return "IONIC_CMD_FW_DOWNLOAD";
case IONIC_CMD_FW_CONTROL:
return "IONIC_CMD_FW_CONTROL";
default:
return "DEVCMD_UNKNOWN";
}
}
int ionic_dev_cmd_wait(struct ionic *ionic, unsigned long max_seconds)
{
struct ionic_dev *idev = &ionic->idev;
unsigned long start_time;
unsigned long max_wait;
unsigned long duration;
int opcode;
int done;
int err;
WARN_ON(in_interrupt());
/* Wait for dev cmd to complete, retrying if we get EAGAIN,
* but don't wait any longer than max_seconds.
*/
max_wait = jiffies + (max_seconds * HZ);
try_again:
start_time = jiffies;
do {
done = ionic_dev_cmd_done(idev);
if (done)
break;
msleep(20);
} while (!done && time_before(jiffies, max_wait));
duration = jiffies - start_time;
opcode = idev->dev_cmd_regs->cmd.cmd.opcode;
dev_dbg(ionic->dev, "DEVCMD %s (%d) done=%d took %ld secs (%ld jiffies)\n",
ionic_opcode_to_str(opcode), opcode,
done, duration / HZ, duration);
if (!done && !time_before(jiffies, max_wait)) {
dev_warn(ionic->dev, "DEVCMD %s (%d) timeout after %ld secs\n",
ionic_opcode_to_str(opcode), opcode, max_seconds);
return -ETIMEDOUT;
}
err = ionic_dev_cmd_status(&ionic->idev);
if (err) {
if (err == IONIC_RC_EAGAIN && !time_after(jiffies, max_wait)) {
dev_err(ionic->dev, "DEV_CMD %s (%d) error, %s (%d) retrying...\n",
ionic_opcode_to_str(opcode), opcode,
ionic_error_to_str(err), err);
msleep(1000);
iowrite32(0, &idev->dev_cmd_regs->done);
iowrite32(1, &idev->dev_cmd_regs->doorbell);
goto try_again;
}
dev_err(ionic->dev, "DEV_CMD %s (%d) error, %s (%d) failed\n",
ionic_opcode_to_str(opcode), opcode,
ionic_error_to_str(err), err);
return ionic_error_to_errno(err);
}
return 0;
}
int ionic_setup(struct ionic *ionic)
{
int err;
err = ionic_dev_setup(ionic);
if (err)
return err;
return 0;
}
int ionic_identify(struct ionic *ionic)
{
struct ionic_identity *ident = &ionic->ident;
struct ionic_dev *idev = &ionic->idev;
size_t sz;
int err;
memset(ident, 0, sizeof(*ident));
ident->drv.os_type = cpu_to_le32(IONIC_OS_TYPE_LINUX);
strncpy(ident->drv.driver_ver_str, IONIC_DRV_VERSION,
sizeof(ident->drv.driver_ver_str) - 1);
mutex_lock(&ionic->dev_cmd_lock);
sz = min(sizeof(ident->drv), sizeof(idev->dev_cmd_regs->data));
memcpy_toio(&idev->dev_cmd_regs->data, &ident->drv, sz);
ionic_dev_cmd_identify(idev, IONIC_IDENTITY_VERSION_1);
err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
if (!err) {
sz = min(sizeof(ident->dev), sizeof(idev->dev_cmd_regs->data));
memcpy_fromio(&ident->dev, &idev->dev_cmd_regs->data, sz);
}
mutex_unlock(&ionic->dev_cmd_lock);
if (err)
goto err_out_unmap;
ionic_debugfs_add_ident(ionic);
return 0;
err_out_unmap:
return err;
}
int ionic_init(struct ionic *ionic)
{
struct ionic_dev *idev = &ionic->idev;
int err;
mutex_lock(&ionic->dev_cmd_lock);
ionic_dev_cmd_init(idev);
err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
mutex_unlock(&ionic->dev_cmd_lock);
return err;
}
int ionic_reset(struct ionic *ionic)
{
struct ionic_dev *idev = &ionic->idev;
int err;
mutex_lock(&ionic->dev_cmd_lock);
ionic_dev_cmd_reset(idev);
err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT);
mutex_unlock(&ionic->dev_cmd_lock);
return err;
}
static int __init ionic_init_module(void)
{
pr_info("%s %s, ver %s\n",
IONIC_DRV_NAME, IONIC_DRV_DESCRIPTION, IONIC_DRV_VERSION);
ionic_debugfs_create();
return ionic_bus_register_driver();
}
static void __exit ionic_cleanup_module(void)
{
ionic_bus_unregister_driver();
ionic_debugfs_destroy();
pr_info("%s removed\n", IONIC_DRV_NAME);
}

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@ -0,0 +1,133 @@
/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB OR BSD-2-Clause */
/* Copyright (c) 2018-2019 Pensando Systems, Inc. All rights reserved. */
#ifndef IONIC_REGS_H
#define IONIC_REGS_H
#include <linux/io.h>
/** struct ionic_intr - interrupt control register set.
* @coal_init: coalesce timer initial value.
* @mask: interrupt mask value.
* @credits: interrupt credit count and return.
* @mask_assert: interrupt mask value on assert.
* @coal: coalesce timer time remaining.
*/
struct ionic_intr {
u32 coal_init;
u32 mask;
u32 credits;
u32 mask_assert;
u32 coal;
u32 rsvd[3];
};
/** enum ionic_intr_mask_vals - valid values for mask and mask_assert.
* @IONIC_INTR_MASK_CLEAR: unmask interrupt.
* @IONIC_INTR_MASK_SET: mask interrupt.
*/
enum ionic_intr_mask_vals {
IONIC_INTR_MASK_CLEAR = 0,
IONIC_INTR_MASK_SET = 1,
};
/** enum ionic_intr_credits_bits - bitwise composition of credits values.
* @IONIC_INTR_CRED_COUNT: bit mask of credit count, no shift needed.
* @IONIC_INTR_CRED_COUNT_SIGNED: bit mask of credit count, including sign bit.
* @IONIC_INTR_CRED_UNMASK: unmask the interrupt.
* @IONIC_INTR_CRED_RESET_COALESCE: reset the coalesce timer.
* @IONIC_INTR_CRED_REARM: unmask the and reset the timer.
*/
enum ionic_intr_credits_bits {
IONIC_INTR_CRED_COUNT = 0x7fffu,
IONIC_INTR_CRED_COUNT_SIGNED = 0xffffu,
IONIC_INTR_CRED_UNMASK = 0x10000u,
IONIC_INTR_CRED_RESET_COALESCE = 0x20000u,
IONIC_INTR_CRED_REARM = (IONIC_INTR_CRED_UNMASK |
IONIC_INTR_CRED_RESET_COALESCE),
};
static inline void ionic_intr_coal_init(struct ionic_intr __iomem *intr_ctrl,
int intr_idx, u32 coal)
{
iowrite32(coal, &intr_ctrl[intr_idx].coal_init);
}
static inline void ionic_intr_mask(struct ionic_intr __iomem *intr_ctrl,
int intr_idx, u32 mask)
{
iowrite32(mask, &intr_ctrl[intr_idx].mask);
}
static inline void ionic_intr_credits(struct ionic_intr __iomem *intr_ctrl,
int intr_idx, u32 cred, u32 flags)
{
if (WARN_ON_ONCE(cred > IONIC_INTR_CRED_COUNT)) {
cred = ioread32(&intr_ctrl[intr_idx].credits);
cred &= IONIC_INTR_CRED_COUNT_SIGNED;
}
iowrite32(cred | flags, &intr_ctrl[intr_idx].credits);
}
static inline void ionic_intr_clean(struct ionic_intr __iomem *intr_ctrl,
int intr_idx)
{
u32 cred;
cred = ioread32(&intr_ctrl[intr_idx].credits);
cred &= IONIC_INTR_CRED_COUNT_SIGNED;
cred |= IONIC_INTR_CRED_RESET_COALESCE;
iowrite32(cred, &intr_ctrl[intr_idx].credits);
}
static inline void ionic_intr_mask_assert(struct ionic_intr __iomem *intr_ctrl,
int intr_idx, u32 mask)
{
iowrite32(mask, &intr_ctrl[intr_idx].mask_assert);
}
/** enum ionic_dbell_bits - bitwise composition of dbell values.
*
* @IONIC_DBELL_QID_MASK: unshifted mask of valid queue id bits.
* @IONIC_DBELL_QID_SHIFT: queue id shift amount in dbell value.
* @IONIC_DBELL_QID: macro to build QID component of dbell value.
*
* @IONIC_DBELL_RING_MASK: unshifted mask of valid ring bits.
* @IONIC_DBELL_RING_SHIFT: ring shift amount in dbell value.
* @IONIC_DBELL_RING: macro to build ring component of dbell value.
*
* @IONIC_DBELL_RING_0: ring zero dbell component value.
* @IONIC_DBELL_RING_1: ring one dbell component value.
* @IONIC_DBELL_RING_2: ring two dbell component value.
* @IONIC_DBELL_RING_3: ring three dbell component value.
*
* @IONIC_DBELL_INDEX_MASK: bit mask of valid index bits, no shift needed.
*/
enum ionic_dbell_bits {
IONIC_DBELL_QID_MASK = 0xffffff,
IONIC_DBELL_QID_SHIFT = 24,
#define IONIC_DBELL_QID(n) \
(((u64)(n) & IONIC_DBELL_QID_MASK) << IONIC_DBELL_QID_SHIFT)
IONIC_DBELL_RING_MASK = 0x7,
IONIC_DBELL_RING_SHIFT = 16,
#define IONIC_DBELL_RING(n) \
(((u64)(n) & IONIC_DBELL_RING_MASK) << IONIC_DBELL_RING_SHIFT)
IONIC_DBELL_RING_0 = 0,
IONIC_DBELL_RING_1 = IONIC_DBELL_RING(1),
IONIC_DBELL_RING_2 = IONIC_DBELL_RING(2),
IONIC_DBELL_RING_3 = IONIC_DBELL_RING(3),
IONIC_DBELL_INDEX_MASK = 0xffff,
};
static inline void ionic_dbell_ring(u64 __iomem *db_page, int qtype, u64 val)
{
writeq(val, &db_page[qtype]);
}
#endif /* IONIC_REGS_H */