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x86: coding style fixes to arch/x86/kernel/cpu/amd.c

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Before:
   total: 42 errors, 26 warnings, 350 lines checked
After:
   total: 0 errors, 26 warnings, 352 lines checked

No code changed:

arch/x86/kernel/cpu/amd.o:

   text	   data	    bss	    dec	    hex	filename
   1936	    328	      0	   2264	    8d8	amd.o.before
   1936	    328	      0	   2264	    8d8	amd.o.after

md5:
   873430a88faaf31bb4bbfe3a2a691e45  amd.o.before.asm
   873430a88faaf31bb4bbfe3a2a691e45  amd.o.after.asm

Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Paolo Ciarrocchi 2008-02-22 23:10:33 +01:00 committed by Ingo Molnar
parent f975182719
commit fb87a298fb
1 changed files with 48 additions and 46 deletions
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56
arch/x86/kernel/cpu/amd.c
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@ -81,7 +81,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
#ifdef CONFIG_SMP
unsigned long long value;
/* Disable TLB flush filter by setting HWCR.FFDIS on K8
/*
* Disable TLB flush filter by setting HWCR.FFDIS on K8
* bit 6 of msr C001_0015
*
* Errata 63 for SH-B3 steppings
@ -102,14 +103,15 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
* no bus pipeline)
*/
/* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
/*
* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
* DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
*/
clear_bit(0*32+31, c->x86_capability);
r = get_model_name(c);
switch(c->x86)
{
switch (c->x86) {
case 4:
/*
* General Systems BIOSen alias the cpu frequency registers
@ -120,23 +122,22 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
#define CBAR_ENB (0x80000000)
#define CBAR_KEY (0X000000CB)
if (c->x86_model==9 || c->x86_model == 10) {
if (c->x86_model == 9 || c->x86_model == 10) {
if (inl (CBAR) & CBAR_ENB)
outl (0 | CBAR_KEY, CBAR);
}
break;
case 5:
if( c->x86_model < 6 )
{
if (c->x86_model < 6) {
/* Based on AMD doc 20734R - June 2000 */
if ( c->x86_model == 0 ) {
if (c->x86_model == 0) {
clear_bit(X86_FEATURE_APIC, c->x86_capability);
set_bit(X86_FEATURE_PGE, c->x86_capability);
}
break;
}
if ( c->x86_model == 6 && c->x86_mask == 1 ) {
if (c->x86_model == 6 && c->x86_mask == 1) {
const int K6_BUG_LOOP = 1000000;
int n;
void (*f_vide)(void);
@ -166,15 +167,15 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
/* K6 with old style WHCR */
if (c->x86_model < 8 ||
(c->x86_model== 8 && c->x86_mask < 8)) {
(c->x86_model == 8 && c->x86_mask < 8)) {
/* We can only write allocate on the low 508Mb */
if(mbytes>508)
mbytes=508;
if (mbytes > 508)
mbytes = 508;
rdmsr(MSR_K6_WHCR, l, h);
if ((l&0x0000FFFF)==0) {
if ((l&0x0000FFFF) == 0) {
unsigned long flags;
l=(1<<0)|((mbytes/4)<<1);
l = (1<<0)|((mbytes/4)<<1);
local_irq_save(flags);
wbinvd();
wrmsr(MSR_K6_WHCR, l, h);
@ -185,17 +186,17 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
break;
}
if ((c->x86_model == 8 && c->x86_mask >7) ||
if ((c->x86_model == 8 && c->x86_mask > 7) ||
c->x86_model == 9 || c->x86_model == 13) {
/* The more serious chips .. */
if(mbytes>4092)
mbytes=4092;
if (mbytes > 4092)
mbytes = 4092;
rdmsr(MSR_K6_WHCR, l, h);
if ((l&0xFFFF0000)==0) {
if ((l&0xFFFF0000) == 0) {
unsigned long flags;
l=((mbytes>>2)<<22)|(1<<16);
l = ((mbytes>>2)<<22)|(1<<16);
local_irq_save(flags);
wbinvd();
wrmsr(MSR_K6_WHCR, l, h);
@ -219,7 +220,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
break;
case 6: /* An Athlon/Duron */
/* Bit 15 of Athlon specific MSR 15, needs to be 0
/*
* Bit 15 of Athlon specific MSR 15, needs to be 0
* to enable SSE on Palomino/Morgan/Barton CPU's.
* If the BIOS didn't enable it already, enable it here.
*/
@ -233,11 +235,12 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
}
}
/* It's been determined by AMD that Athlons since model 8 stepping 1
/*
* It's been determined by AMD that Athlons since model 8 stepping 1
* are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
* As per AMD technical note 27212 0.2
*/
if ((c->x86_model == 8 && c->x86_mask>=1) || (c->x86_model > 8)) {
if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
rdmsr(MSR_K7_CLK_CTL, l, h);
if ((l & 0xfff00000) != 0x20000000) {
printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
@ -264,9 +267,8 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
display_cacheinfo(c);
if (cpuid_eax(0x80000000) >= 0x80000008) {
if (cpuid_eax(0x80000000) >= 0x80000008)
c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
}
#ifdef CONFIG_X86_HT
/*
@ -308,14 +310,14 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
set_bit(X86_FEATURE_MFENCE_RDTSC, c->x86_capability);
}
static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
{
/* AMD errata T13 (order #21922) */
if ((c->x86 == 6)) {
if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */
size = 64;
if (c->x86_model == 4 &&
(c->x86_mask==0 || c->x86_mask==1)) /* Tbird rev A1/A2 */
(c->x86_mask == 0 || c->x86_mask == 1)) /* Tbird rev A1/A2 */
size = 256;
}
return size;