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clk: sunxi-ng: a83t: Fix PLL lock status register offset

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The offset for the PLL lock status register was incorrectly set to
0x208, which actually points to an unused register. The correct
register offset is 0x20c.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Chen-Yu Tsai 2017-05-22 14:25:47 +08:00 committed by Maxime Ripard
parent 05359be117
commit faea8b0e33
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
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@ -28,7 +28,7 @@
#include "ccu-sun8i-a83t.h"
#define CCU_SUN8I_A83T_LOCK_REG 0x208
#define CCU_SUN8I_A83T_LOCK_REG 0x20c
/*
* The CPU PLLs are actually NP clocks, with P being /1 or /4. However