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rt2x00: Update rt2800 register definitions towards latest definitions.
Definitions taken from the latest rt2860 / rt2870 / rt3070 / rt3090 Ralink vendor drivers. Signed-off-by: Gertjan van Wingerde <gwingerde@gmail.com> Acked-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -56,6 +56,7 @@
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#define RF3021 0x0007
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#define RF3022 0x0008
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#define RF3052 0x0009
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#define RF3320 0x000b
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/*
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* Chipset version.
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@ -90,9 +91,15 @@
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#define NUM_TX_QUEUES 4
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/*
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* USB registers.
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* Registers.
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*/
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/*
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* OPT_14: Unknown register used by rt3xxx devices.
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*/
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#define OPT_14_CSR 0x0114
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#define OPT_14_CSR_BIT0 FIELD32(0x00000001)
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/*
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* INT_SOURCE_CSR: Interrupt source register.
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* Write one to clear corresponding bit.
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@ -397,6 +404,31 @@
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*/
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#define EFUSE_DATA3 0x059c
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/*
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* LDO_CFG0
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*/
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#define LDO_CFG0 0x05d4
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#define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
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#define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
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#define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
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#define LDO_CFG0_BGSEL FIELD32(0x03000000)
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#define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
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#define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
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#define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
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/*
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* GPIO_SWITCH
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*/
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#define GPIO_SWITCH 0x05dc
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#define GPIO_SWITCH_0 FIELD32(0x00000001)
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#define GPIO_SWITCH_1 FIELD32(0x00000002)
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#define GPIO_SWITCH_2 FIELD32(0x00000004)
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#define GPIO_SWITCH_3 FIELD32(0x00000008)
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#define GPIO_SWITCH_4 FIELD32(0x00000010)
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#define GPIO_SWITCH_5 FIELD32(0x00000020)
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#define GPIO_SWITCH_6 FIELD32(0x00000040)
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#define GPIO_SWITCH_7 FIELD32(0x00000080)
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/*
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* MAC Control/Status Registers(CSR).
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* Some values are set in TU, whereas 1 TU == 1024 us.
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@ -1491,6 +1523,14 @@ struct mac_iveiv_entry {
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#define BBP4_TX_BF FIELD8(0x01)
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#define BBP4_BANDWIDTH FIELD8(0x18)
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/*
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* BBP 138: Unknown
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*/
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#define BBP138_RX_ADC1 FIELD8(0x02)
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#define BBP138_RX_ADC2 FIELD8(0x04)
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#define BBP138_TX_DAC1 FIELD8(0x20)
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#define BBP138_TX_DAC2 FIELD8(0x40)
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/*
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* RFCSR registers
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* The wordsize of the RFCSR is 8 bits.
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@ -1499,7 +1539,8 @@ struct mac_iveiv_entry {
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/*
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* RFCSR 6:
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*/
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#define RFCSR6_R FIELD8(0x03)
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#define RFCSR6_R1 FIELD8(0x03)
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#define RFCSR6_R2 FIELD8(0x40)
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/*
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* RFCSR 7:
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@ -1511,6 +1552,14 @@ struct mac_iveiv_entry {
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*/
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#define RFCSR12_TX_POWER FIELD8(0x1f)
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/*
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* RFCSR 17:
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*/
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#define RFCSR17_R1 FIELD8(0x07)
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#define RFCSR17_R2 FIELD8(0x08)
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#define RFCSR17_R3 FIELD8(0x20)
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/*
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* RFCSR 22:
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*/
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@ -1603,6 +1652,8 @@ struct mac_iveiv_entry {
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#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
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#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
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#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
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#define EEPROM_NIC_ANT_DIVERSITY FIELD16(0x0800)
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#define EEPROM_NIC_DAC_TEST FIELD16(0x8000)
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/*
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* EEPROM frequency
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@ -797,7 +797,7 @@ static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
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rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
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rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
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rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
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rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
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rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
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rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
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