mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-17 09:43:59 +08:00
Merge branch 'samsung-fb-next' of git://github.com/jingoo/linux into for-linus
Samsung Framebuffer changes for the 3.8 merge window. - The bit definitions of header file are updated. - Some minor typos are fixed. - Some minor bugs of s3c_fb_check_var() are fixed. * 'samsung-fb-next' of git://github.com/jingoo/linux: video: s3c-fb: fix red offset and length for ARGB232 format video: s3c-fb: return an error when bpp is invalid video: s3c-fb: add "drop through" comment video: s3c-fb: use dev_get_drvdata() instead of platform_get_drvdata() video: s3c-fb: use FIMD_V8_VIDTCON0 for EXYNOS5 FIMD video: s3c-fb: fix help message for FB_S3C_DEBUG_REGWRITE video: s3c-fb: fix typo in comment video: s3c-fb: add the bit definitions for VIDCON0_VIDOUT_WB video: s3c-fb: move the bit definitions for DITHMODE register video: s3c-fb: move the bit definitions for WINxMAP and WPALCON register video: s3c-fb: move the bit definitions for VIDINTCON0 register video: s3c-fb: move the address definition for VIDOSD register video: s3c-fb: move the address definitions for VIDTCON registers video: s3c-fb: clean the bit definition for WINCON register
This commit is contained in:
Tomi Valkeinen
commit
fa1f949798
@ -2045,7 +2045,7 @@ config FB_S3C_DEBUG_REGWRITE
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bool "Debug register writes"
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depends on FB_S3C
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---help---
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Show all register writes via printk(KERN_DEBUG)
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Show all register writes via pr_debug()
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config FB_S3C2410
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tristate "S3C2410 LCD framebuffer support"
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@ -189,7 +189,7 @@ struct s3c_fb_vsync {
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/**
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* struct s3c_fb - overall hardware state of the hardware
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* @slock: The spinlock protection for this data sturucture.
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* @slock: The spinlock protection for this data structure.
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* @dev: The device that we bound to, for printing, etc.
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* @bus_clk: The clk (hclk) feeding our interface and possibly pixclk.
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* @lcd_clk: The clk (sclk) feeding pixclk.
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@ -268,10 +268,10 @@ static int s3c_fb_check_var(struct fb_var_screeninfo *var,
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case 8:
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if (sfb->variant.palette[win->index] != 0) {
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/* non palletised, A:1,R:2,G:3,B:2 mode */
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var->red.offset = 4;
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var->red.offset = 5;
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var->green.offset = 2;
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var->blue.offset = 0;
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var->red.length = 5;
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var->red.length = 2;
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var->green.length = 3;
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var->blue.length = 2;
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var->transp.offset = 7;
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@ -288,6 +288,7 @@ static int s3c_fb_check_var(struct fb_var_screeninfo *var,
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/* 666 with one bit alpha/transparency */
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var->transp.offset = 18;
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var->transp.length = 1;
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/* drop through */
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case 18:
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var->bits_per_pixel = 32;
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@ -329,6 +330,7 @@ static int s3c_fb_check_var(struct fb_var_screeninfo *var,
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default:
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dev_err(sfb->dev, "invalid bpp\n");
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return -EINVAL;
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}
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dev_dbg(sfb->dev, "%s: verified parameters\n", __func__);
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@ -1544,8 +1546,7 @@ static int __devexit s3c_fb_remove(struct platform_device *pdev)
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#ifdef CONFIG_PM_SLEEP
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static int s3c_fb_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct s3c_fb *sfb = platform_get_drvdata(pdev);
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struct s3c_fb *sfb = dev_get_drvdata(dev);
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struct s3c_fb_win *win;
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int win_no;
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@ -1572,8 +1573,7 @@ static int s3c_fb_suspend(struct device *dev)
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static int s3c_fb_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct s3c_fb *sfb = platform_get_drvdata(pdev);
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struct s3c_fb *sfb = dev_get_drvdata(dev);
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struct s3c_fb_platdata *pd = sfb->pdata;
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struct s3c_fb_win *win;
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int win_no;
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@ -1623,7 +1623,7 @@ static int s3c_fb_resume(struct device *dev)
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if (!win)
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continue;
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dev_dbg(&pdev->dev, "resuming window %d\n", win_no);
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dev_dbg(dev, "resuming window %d\n", win_no);
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s3c_fb_set_par(win->fbinfo);
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}
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@ -1636,8 +1636,7 @@ static int s3c_fb_resume(struct device *dev)
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#ifdef CONFIG_PM_RUNTIME
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static int s3c_fb_runtime_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct s3c_fb *sfb = platform_get_drvdata(pdev);
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struct s3c_fb *sfb = dev_get_drvdata(dev);
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if (!sfb->variant.has_clksel)
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clk_disable_unprepare(sfb->lcd_clk);
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@ -1649,8 +1648,7 @@ static int s3c_fb_runtime_suspend(struct device *dev)
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static int s3c_fb_runtime_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct s3c_fb *sfb = platform_get_drvdata(pdev);
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struct s3c_fb *sfb = dev_get_drvdata(dev);
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struct s3c_fb_platdata *pd = sfb->pdata;
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clk_prepare_enable(sfb->bus_clk);
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@ -1910,7 +1908,7 @@ static struct s3c_fb_driverdata s3c_fb_data_exynos4 = {
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static struct s3c_fb_driverdata s3c_fb_data_exynos5 = {
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.variant = {
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.nr_windows = 5,
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.vidtcon = VIDTCON0,
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.vidtcon = FIMD_V8_VIDTCON0,
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.wincon = WINCON(0),
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.winmap = WINxMAP(0),
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.keycon = WKEYCON,
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@ -24,12 +24,15 @@
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#define VIDCON0 (0x00)
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#define VIDCON0_INTERLACE (1 << 29)
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#define VIDCON0_VIDOUT_MASK (0x3 << 26)
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#define VIDCON0_VIDOUT_MASK (0x7 << 26)
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#define VIDCON0_VIDOUT_SHIFT (26)
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#define VIDCON0_VIDOUT_RGB (0x0 << 26)
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#define VIDCON0_VIDOUT_TV (0x1 << 26)
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#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
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#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
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#define VIDCON0_VIDOUT_WB_RGB (0x4 << 26)
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#define VIDCON0_VIDOUT_WB_I80_LDI0 (0x6 << 26)
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#define VIDCON0_VIDOUT_WB_I80_LDI1 (0x7 << 26)
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#define VIDCON0_L1_DATA_MASK (0x7 << 23)
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#define VIDCON0_L1_DATA_SHIFT (23)
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@ -77,6 +80,7 @@
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#define VIDCON1_LINECNT_MASK (0x7ff << 16)
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#define VIDCON1_LINECNT_SHIFT (16)
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#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
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#define VIDCON1_FSTATUS_EVEN (1 << 15)
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#define VIDCON1_VSTATUS_MASK (0x3 << 13)
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#define VIDCON1_VSTATUS_SHIFT (13)
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#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
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@ -116,6 +120,7 @@
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/* VIDTCON0 */
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#define VIDTCON0 (0x10)
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#define VIDTCON0_VBPDE_MASK (0xff << 24)
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#define VIDTCON0_VBPDE_SHIFT (24)
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#define VIDTCON0_VBPDE_LIMIT (0xff)
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@ -138,6 +143,7 @@
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/* VIDTCON1 */
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#define VIDTCON1 (0x14)
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#define VIDTCON1_VFPDE_MASK (0xff << 24)
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#define VIDTCON1_VFPDE_SHIFT (24)
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#define VIDTCON1_VFPDE_LIMIT (0xff)
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@ -158,6 +164,7 @@
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#define VIDTCON1_HSPW_LIMIT (0xff)
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#define VIDTCON1_HSPW(_x) ((_x) << 0)
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#define VIDTCON2 (0x18)
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#define VIDTCON2 (0x18)
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#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
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#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
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@ -173,18 +180,27 @@
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/* WINCONx */
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#define WINCON(_win) (0x20 + ((_win) * 4))
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#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
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#define WINCONx_CSCWIDTH_SHIFT (26)
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#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
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#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
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#define WINCONx_ENLOCAL (1 << 22)
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#define WINCONx_BUFSTATUS (1 << 21)
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#define WINCONx_BUFSEL (1 << 20)
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#define WINCONx_BUFAUTOEN (1 << 19)
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#define WINCONx_BITSWP (1 << 18)
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#define WINCONx_BYTSWP (1 << 17)
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#define WINCONx_HAWSWP (1 << 16)
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#define WINCONx_WSWP (1 << 15)
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#define WINCONx_YCbCr (1 << 13)
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#define WINCONx_BURSTLEN_MASK (0x3 << 9)
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#define WINCONx_BURSTLEN_SHIFT (9)
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#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
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#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
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#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
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#define WINCONx_ENWIN (1 << 0)
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#define WINCON0_BPPMODE_MASK (0xf << 2)
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#define WINCON0_BPPMODE_SHIFT (2)
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#define WINCON0_BPPMODE_1BPP (0x0 << 2)
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@ -196,9 +212,8 @@
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#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
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#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
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#define WINCON1_LOCALSEL_CAMIF (1 << 23)
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#define WINCON1_BLD_PIX (1 << 6)
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#define WINCON1_ALPHA_SEL (1 << 1)
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#define WINCON1_BPPMODE_MASK (0xf << 2)
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#define WINCON1_BPPMODE_SHIFT (2)
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#define WINCON1_BPPMODE_1BPP (0x0 << 2)
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@ -216,6 +231,7 @@
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#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
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#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
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#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
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#define WINCON1_ALPHA_SEL (1 << 1)
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/* S5PV210 */
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#define SHADOWCON (0x34)
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@ -225,6 +241,9 @@
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/* Local input channels (windows 0-2) */
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#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))
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/* VIDOSDx */
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#define VIDOSD_BASE (0x40)
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#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
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#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
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#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
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@ -293,6 +312,7 @@
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/* Interrupt controls and status */
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#define VIDINTCON0 (0x130)
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#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
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#define VIDINTCON0_FIFOINTERVAL_SHIFT (20)
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#define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f)
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@ -321,6 +341,9 @@
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#define VIDINTCON0_FIFIOSEL_SHIFT (5)
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#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
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#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
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#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
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#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
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#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
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#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
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#define VIDINTCON0_FIFOLEVEL_SHIFT (2)
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@ -357,16 +380,39 @@
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#define WxKEYCON1_COLVAL_LIMIT (0xffffff)
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#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
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/* Dithering control */
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#define DITHMODE (0x170)
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#define DITHMODE_R_POS_MASK (0x3 << 5)
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#define DITHMODE_R_POS_SHIFT (5)
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#define DITHMODE_R_POS_8BIT (0x0 << 5)
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#define DITHMODE_R_POS_6BIT (0x1 << 5)
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#define DITHMODE_R_POS_5BIT (0x2 << 5)
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#define DITHMODE_G_POS_MASK (0x3 << 3)
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#define DITHMODE_G_POS_SHIFT (3)
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#define DITHMODE_G_POS_8BIT (0x0 << 3)
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#define DITHMODE_G_POS_6BIT (0x1 << 3)
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#define DITHMODE_G_POS_5BIT (0x2 << 3)
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#define DITHMODE_B_POS_MASK (0x3 << 1)
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#define DITHMODE_B_POS_SHIFT (1)
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#define DITHMODE_B_POS_8BIT (0x0 << 1)
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#define DITHMODE_B_POS_6BIT (0x1 << 1)
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#define DITHMODE_B_POS_5BIT (0x2 << 1)
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#define DITHMODE_DITH_EN (1 << 0)
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/* Window blanking (MAP) */
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#define WINxMAP(_win) (0x180 + ((_win) * 4))
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#define WINxMAP_MAP (1 << 24)
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#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
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#define WINxMAP_MAP_COLOUR_SHIFT (0)
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#define WINxMAP_MAP_COLOUR_LIMIT (0xffffff)
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#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
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/* Winodw palette control */
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#define WPALCON (0x1A0)
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#define WPALCON_PAL_UPDATE (1 << 9)
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#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
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#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
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#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
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#define WPALCON_W1PAL_MASK (0x7 << 3)
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#define WPALCON_W1PAL_SHIFT (3)
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#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
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@ -376,7 +422,6 @@
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#define WPALCON_W1PAL_18BPP (0x4 << 3)
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#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
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#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
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#define WPALCON_W0PAL_MASK (0x7 << 0)
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#define WPALCON_W0PAL_SHIFT (0)
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#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
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@ -394,115 +439,6 @@
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#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
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#define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */
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#define VIDCON1_FSTATUS_EVEN (1 << 15)
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/* Video timing controls */
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#define VIDTCON0 (0x10)
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#define VIDTCON1 (0x14)
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#define VIDTCON2 (0x18)
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/* Window position controls */
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#define WINCON(_win) (0x20 + ((_win) * 4))
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/* OSD1 and OSD4 do not have register D */
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#define VIDOSD_BASE (0x40)
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#define VIDINTCON0 (0x130)
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/* WINCONx */
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#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
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#define WINCONx_CSCWIDTH_SHIFT (26)
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#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
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#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
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#define WINCONx_ENLOCAL (1 << 22)
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#define WINCONx_BUFSTATUS (1 << 21)
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#define WINCONx_BUFSEL (1 << 20)
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#define WINCONx_BUFAUTOEN (1 << 19)
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#define WINCONx_YCbCr (1 << 13)
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#define WINCON1_LOCALSEL_CAMIF (1 << 23)
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#define WINCON2_LOCALSEL_CAMIF (1 << 23)
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#define WINCON2_BLD_PIX (1 << 6)
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#define WINCON2_ALPHA_SEL (1 << 1)
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#define WINCON2_BPPMODE_MASK (0xf << 2)
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#define WINCON2_BPPMODE_SHIFT (2)
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#define WINCON2_BPPMODE_1BPP (0x0 << 2)
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#define WINCON2_BPPMODE_2BPP (0x1 << 2)
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#define WINCON2_BPPMODE_4BPP (0x2 << 2)
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#define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2)
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#define WINCON2_BPPMODE_16BPP_565 (0x5 << 2)
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#define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2)
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#define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2)
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#define WINCON2_BPPMODE_18BPP_666 (0x8 << 2)
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#define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2)
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#define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2)
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#define WINCON2_BPPMODE_24BPP_888 (0xb << 2)
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#define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2)
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#define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2)
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#define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2)
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#define WINCON3_BLD_PIX (1 << 6)
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#define WINCON3_ALPHA_SEL (1 << 1)
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#define WINCON3_BPPMODE_MASK (0xf << 2)
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#define WINCON3_BPPMODE_SHIFT (2)
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#define WINCON3_BPPMODE_1BPP (0x0 << 2)
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#define WINCON3_BPPMODE_2BPP (0x1 << 2)
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#define WINCON3_BPPMODE_4BPP (0x2 << 2)
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#define WINCON3_BPPMODE_16BPP_565 (0x5 << 2)
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#define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2)
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#define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2)
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#define WINCON3_BPPMODE_18BPP_666 (0x8 << 2)
|
||||
#define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2)
|
||||
#define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2)
|
||||
#define WINCON3_BPPMODE_24BPP_888 (0xb << 2)
|
||||
#define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2)
|
||||
#define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2)
|
||||
#define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2)
|
||||
|
||||
#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
|
||||
#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
|
||||
#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
|
||||
|
||||
#define DITHMODE (0x170)
|
||||
#define WINxMAP(_win) (0x180 + ((_win) * 4))
|
||||
|
||||
|
||||
#define DITHMODE_R_POS_MASK (0x3 << 5)
|
||||
#define DITHMODE_R_POS_SHIFT (5)
|
||||
#define DITHMODE_R_POS_8BIT (0x0 << 5)
|
||||
#define DITHMODE_R_POS_6BIT (0x1 << 5)
|
||||
#define DITHMODE_R_POS_5BIT (0x2 << 5)
|
||||
|
||||
#define DITHMODE_G_POS_MASK (0x3 << 3)
|
||||
#define DITHMODE_G_POS_SHIFT (3)
|
||||
#define DITHMODE_G_POS_8BIT (0x0 << 3)
|
||||
#define DITHMODE_G_POS_6BIT (0x1 << 3)
|
||||
#define DITHMODE_G_POS_5BIT (0x2 << 3)
|
||||
|
||||
#define DITHMODE_B_POS_MASK (0x3 << 1)
|
||||
#define DITHMODE_B_POS_SHIFT (1)
|
||||
#define DITHMODE_B_POS_8BIT (0x0 << 1)
|
||||
#define DITHMODE_B_POS_6BIT (0x1 << 1)
|
||||
#define DITHMODE_B_POS_5BIT (0x2 << 1)
|
||||
|
||||
#define DITHMODE_DITH_EN (1 << 0)
|
||||
|
||||
#define WPALCON (0x1A0)
|
||||
|
||||
/* Palette control */
|
||||
/* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
|
||||
* but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
|
||||
#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
|
||||
#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
|
||||
#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
|
||||
|
||||
|
||||
/* Notes on per-window bpp settings
|
||||
*
|
||||
|
||||
Loading…
Reference in New Issue
Block a user