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net: ipa: define GSI interrupt types with an enum

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Define the GSI interrupt types with an enumerated type whose values
are the bit positions representing each interrupt type.  Include a
short comment describing how each interrupt type is used.

Build up the enabled interrupt mask explicitly in gsi_irq_enable(),
and get rid of the definition of GSI_CNTXT_TYPE_IRQ_MSK_ALL.

Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Alex Elder 2020-11-05 12:13:58 -06:00 committed by Jakub Kicinski
parent a054539db1
commit f9b28804ab
2 changed files with 22 additions and 18 deletions
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21
drivers/net/ipa/gsi.c
View File

@ -253,10 +253,12 @@ static void gsi_irq_enable(struct gsi *gsi)
{
u32 val;
/* We don't use inter-EE channel or event interrupts */
val = GSI_CNTXT_TYPE_IRQ_MSK_ALL;
val &= ~INTER_EE_CH_CTRL_FMASK;
val &= ~INTER_EE_EV_CTRL_FMASK;
val = BIT(GSI_CH_CTRL);
val |= BIT(GSI_EV_CTRL);
val |= BIT(GSI_GLOB_EE);
val |= BIT(GSI_IEOB);
/* We don't use inter-EE channel or event control interrupts */
val |= BIT(GSI_GENERAL);
iowrite32(val, gsi->virt + GSI_CNTXT_TYPE_IRQ_MSK_OFFSET);
val = GENMASK(gsi->channel_count - 1, 0);
@ -1130,6 +1132,7 @@ static irqreturn_t gsi_isr(int irq, void *dev_id)
u32 intr_mask;
u32 cnt = 0;
/* enum gsi_irq_type_id defines GSI interrupt types */
while ((intr_mask = ioread32(gsi->virt + GSI_CNTXT_TYPE_IRQ_OFFSET))) {
/* intr_mask contains bitmask of pending GSI interrupts */
do {
@ -1138,19 +1141,19 @@ static irqreturn_t gsi_isr(int irq, void *dev_id)
intr_mask ^= gsi_intr;
switch (gsi_intr) {
case CH_CTRL_FMASK:
case BIT(GSI_CH_CTRL):
gsi_isr_chan_ctrl(gsi);
break;
case EV_CTRL_FMASK:
case BIT(GSI_EV_CTRL):
gsi_isr_evt_ctrl(gsi);
break;
case GLOB_EE_FMASK:
case BIT(GSI_GLOB_EE):
gsi_isr_glob_ee(gsi);
break;
case IEOB_FMASK:
case BIT(GSI_IEOB):
gsi_isr_ieob(gsi);
break;
case GENERAL_FMASK:
case BIT(GSI_GENERAL):
gsi_isr_general(gsi);
break;
default:

19
drivers/net/ipa/gsi_reg.h
View File

@ -262,15 +262,16 @@
GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP)
#define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \
(0x0001f088 + 0x4000 * (ee))
/* The masks below are used for the TYPE_IRQ and TYPE_IRQ_MASK registers */
#define CH_CTRL_FMASK GENMASK(0, 0)
#define EV_CTRL_FMASK GENMASK(1, 1)
#define GLOB_EE_FMASK GENMASK(2, 2)
#define IEOB_FMASK GENMASK(3, 3)
#define INTER_EE_CH_CTRL_FMASK GENMASK(4, 4)
#define INTER_EE_EV_CTRL_FMASK GENMASK(5, 5)
#define GENERAL_FMASK GENMASK(6, 6)
#define GSI_CNTXT_TYPE_IRQ_MSK_ALL GENMASK(6, 0)
/* Values here are bit positions in the TYPE_IRQ and TYPE_IRQ_MSK registers */
enum gsi_irq_type_id {
GSI_CH_CTRL = 0, /* channel allocation, etc. */
GSI_EV_CTRL = 1, /* event ring allocation, etc. */
GSI_GLOB_EE = 2, /* global/general event */
GSI_IEOB = 3, /* TRE completion */
GSI_INTER_EE_CH_CTRL = 4, /* remote-issued stop/reset (unused) */
GSI_INTER_EE_EV_CTRL = 5, /* remote-issued event reset (unused) */
GSI_GENERAL = 6, /* general-purpose event */
};
#define GSI_CNTXT_SRC_CH_IRQ_OFFSET \
GSI_EE_N_CNTXT_SRC_CH_IRQ_OFFSET(GSI_EE_AP)