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Code

drm/radeon: add dpm UVD handling for evergreen/btc asics

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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2013-06-26 00:35:16 -04:00
parent 7c464f68b3
commit f85392bcf9
7 changed files with 107 additions and 14 deletions
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62
drivers/gpu/drm/radeon/btc_dpm.c
View File

@ -1510,6 +1510,46 @@ static int btc_init_smc_table(struct radeon_device *rdev)
pi->sram_end);
}
static void btc_set_at_for_uvd(struct radeon_device *rdev)
{
struct rv7xx_power_info *pi = rv770_get_pi(rdev);
struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
int idx = 0;
if (r600_is_uvd_state(radeon_new_state->class, radeon_new_state->class2))
idx = 1;
if ((idx == 1) && !eg_pi->smu_uvd_hs) {
pi->rlp = 10;
pi->rmp = 100;
pi->lhp = 100;
pi->lmp = 10;
} else {
pi->rlp = eg_pi->ats[idx].rlp;
pi->rmp = eg_pi->ats[idx].rmp;
pi->lhp = eg_pi->ats[idx].lhp;
pi->lmp = eg_pi->ats[idx].lmp;
}
}
static void btc_notify_uvd_to_smc(struct radeon_device *rdev)
{
struct radeon_ps *radeon_new_state = rdev->pm.dpm.requested_ps;
struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
if (r600_is_uvd_state(radeon_new_state->class, radeon_new_state->class2)) {
rv770_write_smc_soft_register(rdev,
RV770_SMC_SOFT_REGISTER_uvd_enabled, 1);
eg_pi->uvd_enabled = true;
} else {
rv770_write_smc_soft_register(rdev,
RV770_SMC_SOFT_REGISTER_uvd_enabled, 0);
eg_pi->uvd_enabled = false;
}
}
static int btc_reset_to_default(struct radeon_device *rdev)
{
if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) != PPSMC_Result_OK)
@ -1880,7 +1920,11 @@ int btc_dpm_set_power_state(struct radeon_device *rdev)
if (eg_pi->pcie_performance_request)
cypress_notify_link_speed_change_before_state_change(rdev);
rv770_set_uvd_clock_before_set_eng_clock(rdev);
rv770_halt_smc(rdev);
btc_set_at_for_uvd(rdev);
if (eg_pi->smu_uvd_hs)
btc_notify_uvd_to_smc(rdev);
cypress_upload_sw_state(rdev);
if (eg_pi->dynamic_ac_timing)
@ -1890,6 +1934,7 @@ int btc_dpm_set_power_state(struct radeon_device *rdev)
rv770_resume_smc(rdev);
rv770_set_sw_state(rdev);
rv770_set_uvd_clock_after_set_eng_clock(rdev);
if (eg_pi->pcie_performance_request)
cypress_notify_link_speed_change_after_state_change(rdev);
@ -2098,6 +2143,23 @@ int btc_dpm_init(struct radeon_device *rdev)
pi->mclk_edc_enable_threshold = 40000;
eg_pi->mclk_edc_wr_enable_threshold = 40000;
pi->rlp = RV770_RLP_DFLT;
pi->rmp = RV770_RMP_DFLT;
pi->lhp = RV770_LHP_DFLT;
pi->lmp = RV770_LMP_DFLT;
eg_pi->ats[0].rlp = RV770_RLP_DFLT;
eg_pi->ats[0].rmp = RV770_RMP_DFLT;
eg_pi->ats[0].lhp = RV770_LHP_DFLT;
eg_pi->ats[0].lmp = RV770_LMP_DFLT;
eg_pi->ats[1].rlp = BTC_RLP_UVD_DFLT;
eg_pi->ats[1].rmp = BTC_RMP_UVD_DFLT;
eg_pi->ats[1].lhp = BTC_LHP_UVD_DFLT;
eg_pi->ats[1].lmp = BTC_LMP_UVD_DFLT;
eg_pi->smu_uvd_hs = true;
pi->voltage_control =
radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC);

4
drivers/gpu/drm/radeon/btc_dpm.h
View File

@ -23,6 +23,10 @@
#ifndef __BTC_DPM_H__
#define __BTC_DPM_H__
#define BTC_RLP_UVD_DFLT 20
#define BTC_RMP_UVD_DFLT 50
#define BTC_LHP_UVD_DFLT 50
#define BTC_LMP_UVD_DFLT 20
#define BARTS_MGCGCGTSSMCTRL_DFLT 0x81944000
#define TURKS_MGCGCGTSSMCTRL_DFLT 0x6e944000
#define CAICOS_MGCGCGTSSMCTRL_DFLT 0x46944040

10
drivers/gpu/drm/radeon/cypress_dpm.c
View File

@ -690,7 +690,8 @@ int cypress_convert_power_level_to_smc(struct radeon_device *rdev,
level->mcFlags = 0;
if (pi->mclk_stutter_mode_threshold &&
(pl->mclk <= pi->mclk_stutter_mode_threshold)) {
(pl->mclk <= pi->mclk_stutter_mode_threshold) &&
!eg_pi->uvd_enabled) {
level->mcFlags |= SMC_MC_STUTTER_EN;
if (eg_pi->sclk_deep_sleep)
level->stateFlags |= PPSMC_STATEFLAG_AUTO_PULSE_SKIP;
@ -1938,6 +1939,7 @@ int cypress_dpm_set_power_state(struct radeon_device *rdev)
if (eg_pi->pcie_performance_request)
cypress_notify_link_speed_change_before_state_change(rdev);
rv770_set_uvd_clock_before_set_eng_clock(rdev);
rv770_halt_smc(rdev);
cypress_upload_sw_state(rdev);
@ -1948,6 +1950,7 @@ int cypress_dpm_set_power_state(struct radeon_device *rdev)
rv770_resume_smc(rdev);
rv770_set_sw_state(rdev);
rv770_set_uvd_clock_after_set_eng_clock(rdev);
if (eg_pi->pcie_performance_request)
cypress_notify_link_speed_change_after_state_change(rdev);
@ -2012,6 +2015,11 @@ int cypress_dpm_init(struct radeon_device *rdev)
pi->mclk_edc_enable_threshold = 40000;
eg_pi->mclk_edc_wr_enable_threshold = 40000;
pi->rlp = RV770_RLP_DFLT;
pi->rmp = RV770_RMP_DFLT;
pi->lhp = RV770_LHP_DFLT;
pi->lmp = RV770_LMP_DFLT;
pi->voltage_control =
radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC);

10
drivers/gpu/drm/radeon/cypress_dpm.h
View File

@ -51,6 +51,13 @@ struct evergreen_arb_registers {
u32 mc_arb_burst_time;
};
struct at {
u32 rlp;
u32 rmp;
u32 lhp;
u32 lmp;
};
struct evergreen_power_info {
/* must be first! */
struct rv7xx_power_info rv7xx;
@ -66,6 +73,8 @@ struct evergreen_power_info {
bool sclk_deep_sleep;
bool dll_default_on;
bool ls_clock_gating;
bool smu_uvd_hs;
bool uvd_enabled;
/* stored values */
u16 acpi_vddci;
u8 mvdd_high_index;
@ -76,6 +85,7 @@ struct evergreen_power_info {
struct atom_voltage_table vddci_voltage_table;
struct evergreen_arb_registers bootup_arb_registers;
struct evergreen_ulv_param ulv;
struct at ats[2];
/* smc offsets */
u16 mc_reg_table_start;
};

30
drivers/gpu/drm/radeon/rv770_dpm.c
View File

@ -265,22 +265,21 @@ int rv770_populate_smc_t(struct radeon_device *rdev,
l[0] = 0;
r[2] = 100;
a_n = (int)state->medium.sclk * RV770_LMP_DFLT +
(int)state->low.sclk * (R600_AH_DFLT - RV770_RLP_DFLT);
a_d = (int)state->low.sclk * (100 - (int)RV770_RLP_DFLT) +
(int)state->medium.sclk * RV770_LMP_DFLT;
a_n = (int)state->medium.sclk * pi->lmp +
(int)state->low.sclk * (R600_AH_DFLT - pi->rlp);
a_d = (int)state->low.sclk * (100 - (int)pi->rlp) +
(int)state->medium.sclk * pi->lmp;
l[1] = (u8)(RV770_LMP_DFLT - (int)RV770_LMP_DFLT * a_n / a_d);
r[0] = (u8)(RV770_RLP_DFLT + (100 - (int)RV770_RLP_DFLT) * a_n / a_d);
l[1] = (u8)(pi->lmp - (int)pi->lmp * a_n / a_d);
r[0] = (u8)(pi->rlp + (100 - (int)pi->rlp) * a_n / a_d);
a_n = (int)state->high.sclk * RV770_LHP_DFLT +
(int)state->medium.sclk *
(R600_AH_DFLT - RV770_RMP_DFLT);
a_d = (int)state->medium.sclk * (100 - (int)RV770_RMP_DFLT) +
(int)state->high.sclk * RV770_LHP_DFLT;
a_n = (int)state->high.sclk * pi->lhp + (int)state->medium.sclk *
(R600_AH_DFLT - pi->rmp);
a_d = (int)state->medium.sclk * (100 - (int)pi->rmp) +
(int)state->high.sclk * pi->lhp;
l[2] = (u8)(RV770_LHP_DFLT - (int)RV770_LHP_DFLT * a_n / a_d);
r[1] = (u8)(RV770_RMP_DFLT + (100 - (int)RV770_RMP_DFLT) * a_n / a_d);
l[2] = (u8)(pi->lhp - (int)pi->lhp * a_n / a_d);
r[1] = (u8)(pi->rmp + (100 - (int)pi->rmp) * a_n / a_d);
for (i = 0; i < (RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1); i++) {
a_t = CG_R(r[i] * pi->bsp / 200) | CG_L(l[i] * pi->bsp / 200);
@ -2281,6 +2280,11 @@ int rv770_dpm_init(struct radeon_device *rdev)
pi->mclk_strobe_mode_threshold = 30000;
pi->mclk_edc_enable_threshold = 30000;
pi->rlp = RV770_RLP_DFLT;
pi->rmp = RV770_RMP_DFLT;
pi->lhp = RV770_LHP_DFLT;
pi->lmp = RV770_LMP_DFLT;
pi->voltage_control =
radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC);

4
drivers/gpu/drm/radeon/rv770_dpm.h
View File

@ -126,6 +126,10 @@ struct rv7xx_power_info {
u32 pasi;
u32 vrc;
u32 restricted_levels;
u32 rlp;
u32 rmp;
u32 lhp;
u32 lmp;
/* smc offsets */
u16 state_table_start;
u16 soft_regs_start;

1
drivers/gpu/drm/radeon/rv770_smc.h
View File

@ -184,6 +184,7 @@ typedef struct RV770_SMC_STATETABLE RV770_SMC_STATETABLE;
#define RV770_SMC_SOFT_REGISTER_mvdd_chg_time 0x68
#define RV770_SMC_SOFT_REGISTER_mclk_switch_lim 0x78
#define RV770_SMC_SOFT_REGISTER_mc_block_delay 0x90
#define RV770_SMC_SOFT_REGISTER_uvd_enabled 0x9C
#define RV770_SMC_SOFT_REGISTER_is_asic_lombok 0xA0
int rv770_set_smc_sram_address(struct radeon_device *rdev,