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mvebu drivers for 4.9 (part 1)
- Add pinctrl and clk support for the Orion5x SoC mv88f5181 variant -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iEYEABECAAYFAlfiWTAACgkQCwYYjhRyO9X3ZQCfdOuvxXIajKkmxgvVwNgzEeLF GEIAn1LYY/vmNikPhxH4O2FBi/9NBdZM =GrPA -----END PGP SIGNATURE----- Merge tag 'mvebu-drivers-4.9-1' of git://git.infradead.org/linux-mvebu into next/drivers Pull "mvebu drivers for 4.9 (part 1)" from Gregory CLEMENT: - Add pinctrl and clk support for the Orion5x SoC mv88f5181 variant * tag 'mvebu-drivers-4.9-1' of git://git.infradead.org/linux-mvebu: pinctrl: mvebu: orion5x: Generalise mv88f5181l support for 88f5181 clk: mvebu: Add clk support for the orion5x SoC mv88f5181
This commit is contained in:
Arnd Bergmann
commit
f5f8aaf98d
@ -52,6 +52,7 @@ Required properties:
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"marvell,dove-core-clock" - for Dove SoC core clocks
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"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
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"marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
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"marvell,mv88f5181-core-clock" - for Orion MV88F5181 SoC
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"marvell,mv88f5182-core-clock" - for Orion MV88F5182 SoC
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"marvell,mv88f5281-core-clock" - for Orion MV88F5281 SoC
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"marvell,mv88f6183-core-clock" - for Orion MV88F6183 SoC
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@ -4,7 +4,9 @@ Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
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part and usage.
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Required properties:
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- compatible: "marvell,88f5181l-pinctrl", "marvell,88f5182-pinctrl",
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- compatible: "marvell,88f5181-pinctrl",
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"marvell,88f5181l-pinctrl",
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"marvell,88f5182-pinctrl",
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"marvell,88f5281-pinctrl"
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- reg: two register areas, the first one describing the first two
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@ -20,6 +20,76 @@ static const struct coreclk_ratio orion_coreclk_ratios[] __initconst = {
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{ .id = 0, .name = "ddrclk", }
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};
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/*
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* Orion 5181
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*/
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#define SAR_MV88F5181_TCLK_FREQ 8
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#define SAR_MV88F5181_TCLK_FREQ_MASK 0x3
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static u32 __init mv88f5181_get_tclk_freq(void __iomem *sar)
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{
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u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) &
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SAR_MV88F5181_TCLK_FREQ_MASK;
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if (opt == 0)
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return 133333333;
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else if (opt == 1)
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return 150000000;
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else if (opt == 2)
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return 166666667;
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else
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return 0;
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}
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#define SAR_MV88F5181_CPU_FREQ 4
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#define SAR_MV88F5181_CPU_FREQ_MASK 0xf
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static u32 __init mv88f5181_get_cpu_freq(void __iomem *sar)
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{
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u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
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SAR_MV88F5181_CPU_FREQ_MASK;
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if (opt == 0)
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return 333333333;
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else if (opt == 1 || opt == 2)
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return 400000000;
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else if (opt == 3)
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return 500000000;
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else
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return 0;
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}
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static void __init mv88f5181_get_clk_ratio(void __iomem *sar, int id,
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int *mult, int *div)
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{
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u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) &
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SAR_MV88F5181_CPU_FREQ_MASK;
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if (opt == 0 || opt == 1) {
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*mult = 1;
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*div = 2;
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} else if (opt == 2 || opt == 3) {
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*mult = 1;
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*div = 3;
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} else {
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*mult = 0;
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*div = 1;
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}
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}
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static const struct coreclk_soc_desc mv88f5181_coreclks = {
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.get_tclk_freq = mv88f5181_get_tclk_freq,
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.get_cpu_freq = mv88f5181_get_cpu_freq,
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.get_clk_ratio = mv88f5181_get_clk_ratio,
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.ratios = orion_coreclk_ratios,
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.num_ratios = ARRAY_SIZE(orion_coreclk_ratios),
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};
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static void __init mv88f5181_clk_init(struct device_node *np)
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{
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return mvebu_coreclk_setup(np, &mv88f5181_coreclks);
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}
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CLK_OF_DECLARE(mv88f5181_clk, "marvell,mv88f5181-core-clock", mv88f5181_clk_init);
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/*
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* Orion 5182
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*/
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@ -64,11 +64,11 @@ static int orion_mpp_ctrl_set(unsigned pid, unsigned long config)
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return 0;
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}
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#define V(f5181l, f5182, f5281) \
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((f5181l << 0) | (f5182 << 1) | (f5281 << 2))
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#define V(f5181, f5182, f5281) \
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((f5181 << 0) | (f5182 << 1) | (f5281 << 2))
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enum orion_variant {
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V_5181L = V(1, 0, 0),
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V_5181 = V(1, 0, 0),
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V_5182 = V(0, 1, 0),
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V_5281 = V(0, 0, 1),
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V_ALL = V(1, 1, 1),
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@ -103,13 +103,13 @@ static struct mvebu_mpp_mode orion_mpp_modes[] = {
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x2, "pci", "req5", V_ALL),
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MPP_VAR_FUNCTION(0x4, "nand", "re0", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181L),
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MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181),
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MPP_VAR_FUNCTION(0x5, "sata0", "act", V_5182)),
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MPP_MODE(7,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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MPP_VAR_FUNCTION(0x2, "pci", "gnt5", V_ALL),
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MPP_VAR_FUNCTION(0x4, "nand", "we0", V_5182 | V_5281),
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MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181L),
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MPP_VAR_FUNCTION(0x5, "pci-1", "clk", V_5181),
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MPP_VAR_FUNCTION(0x5, "sata1", "act", V_5182)),
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MPP_MODE(8,
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MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_ALL),
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@ -165,7 +165,7 @@ static struct mvebu_mpp_ctrl orion_mpp_controls[] = {
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MPP_FUNC_CTRL(0, 19, NULL, orion_mpp_ctrl),
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};
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static struct pinctrl_gpio_range mv88f5181l_gpio_ranges[] = {
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static struct pinctrl_gpio_range mv88f5181_gpio_ranges[] = {
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MPP_GPIO_RANGE(0, 0, 0, 16),
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};
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@ -177,14 +177,14 @@ static struct pinctrl_gpio_range mv88f5281_gpio_ranges[] = {
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MPP_GPIO_RANGE(0, 0, 0, 16),
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};
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static struct mvebu_pinctrl_soc_info mv88f5181l_info = {
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.variant = V_5181L,
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static struct mvebu_pinctrl_soc_info mv88f5181_info = {
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.variant = V_5181,
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.controls = orion_mpp_controls,
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.ncontrols = ARRAY_SIZE(orion_mpp_controls),
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.modes = orion_mpp_modes,
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.nmodes = ARRAY_SIZE(orion_mpp_modes),
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.gpioranges = mv88f5181l_gpio_ranges,
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.ngpioranges = ARRAY_SIZE(mv88f5181l_gpio_ranges),
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.gpioranges = mv88f5181_gpio_ranges,
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.ngpioranges = ARRAY_SIZE(mv88f5181_gpio_ranges),
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};
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static struct mvebu_pinctrl_soc_info mv88f5182_info = {
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@ -212,7 +212,8 @@ static struct mvebu_pinctrl_soc_info mv88f5281_info = {
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* muxing, they are identical.
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*/
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static const struct of_device_id orion_pinctrl_of_match[] = {
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{ .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181l_info },
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{ .compatible = "marvell,88f5181-pinctrl", .data = &mv88f5181_info },
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{ .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181_info },
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{ .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info },
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{ .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info },
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{ }
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