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powerpc/mm: Cleanup bits definition between hash and radix.

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Define everything based on bits present in pgtable.h. This will help in easily
identifying overlapping bits between hash/radix.

No functional change with this patch.

Reviewed-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Aneesh Kumar K.V 2017-03-21 22:59:53 +05:30 committed by Michael Ellerman
parent 98beda74de
commit f5bd0fdc0c
4 changed files with 17 additions and 12 deletions
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4
arch/powerpc/include/asm/book3s/64/hash-64k.h
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@ -6,6 +6,10 @@
#define H_PUD_INDEX_SIZE 5
#define H_PGD_INDEX_SIZE 12
/*
* 64k aligned address free up few of the lower bits of RPN for us
* We steal that here. For more deatils look at pte_pfn/pfn_pte()
*/
#define H_PAGE_COMBO 0x00001000 /* this is a combo 4k page */
#define H_PAGE_4K_PFN 0x00002000 /* PFN is for a single 4k page */
/*

9
arch/powerpc/include/asm/book3s/64/hash.h
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@ -13,12 +13,13 @@
* We could create separate kernel read-only if we used the 3 PP bits
* combinations that newer processors provide but we currently don't.
*/
#define H_PAGE_BUSY 0x00800 /* software: PTE & hash are busy */
#define H_PAGE_BUSY _RPAGE_SW1 /* software: PTE & hash are busy */
#define H_PTE_NONE_MASK _PAGE_HPTEFLAGS
#define H_PAGE_F_GIX_SHIFT 57
#define H_PAGE_F_GIX (7ul << 57) /* HPTE index within HPTEG */
#define H_PAGE_F_SECOND (1ul << 60) /* HPTE is in 2ndary HPTEG */
#define H_PAGE_HASHPTE (1ul << 61) /* PTE has associated HPTE */
/* (7ul << 57) HPTE index within HPTEG */
#define H_PAGE_F_GIX (_RPAGE_RSV2 | _RPAGE_RSV3 | _RPAGE_RSV4)
#define H_PAGE_F_SECOND _RPAGE_RSV1 /* HPTE is in 2ndary HPTEG */
#define H_PAGE_HASHPTE _RPAGE_SW0 /* PTE has associated HPTE */
#ifdef CONFIG_PPC_64K_PAGES
#include <asm/book3s/64/hash-64k.h>

10
arch/powerpc/include/asm/book3s/64/pgtable.h
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@ -44,14 +44,8 @@
#endif
#define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
/*
* For P9 DD1 only, we need to track whether the pte's huge.
*/
#define _PAGE_LARGE _RPAGE_RSV1
#define _PAGE_PTE (1ul << 62) /* distinguishes PTEs from pointers */
#define _PAGE_PRESENT (1ul << 63) /* pte contains a translation */
#define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */
#define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */
/*
* Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
* Instead of fixing all of them, add an alternate define which

6
arch/powerpc/include/asm/book3s/64/radix.h
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@ -11,6 +11,12 @@
#include <asm/book3s/64/radix-4k.h>
#endif
/*
* For P9 DD1 only, we need to track whether the pte's huge.
*/
#define _PAGE_LARGE _RPAGE_RSV1
#ifndef __ASSEMBLY__
#include <asm/book3s/64/tlbflush-radix.h>
#include <asm/cpu_has_feature.h>