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ARM: module: correctly relocate instructions in BE8
When in BE8 mode, our instructions are not in the same ordering as the data, so use <asm/opcodes.h> to take this into account. Note, also requires modules to be built --be8 Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by: Dave Martin <Dave.Martin@arm.com>
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@ -24,6 +24,7 @@
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#include <asm/sections.h>
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#include <asm/smp_plat.h>
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#include <asm/unwind.h>
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#include <asm/opcodes.h>
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#ifdef CONFIG_XIP_KERNEL
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/*
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@ -60,6 +61,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
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Elf32_Sym *sym;
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const char *symname;
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s32 offset;
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u32 tmp;
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#ifdef CONFIG_THUMB2_KERNEL
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u32 upper, lower, sign, j1, j2;
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#endif
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@ -95,7 +97,8 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
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case R_ARM_PC24:
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case R_ARM_CALL:
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case R_ARM_JUMP24:
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offset = (*(u32 *)loc & 0x00ffffff) << 2;
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offset = __mem_to_opcode_arm(*(u32 *)loc);
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offset = (offset & 0x00ffffff) << 2;
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if (offset & 0x02000000)
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offset -= 0x04000000;
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@ -111,9 +114,10 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
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}
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offset >>= 2;
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offset &= 0x00ffffff;
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*(u32 *)loc &= 0xff000000;
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*(u32 *)loc |= offset & 0x00ffffff;
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*(u32 *)loc &= __opcode_to_mem_arm(0xff000000);
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*(u32 *)loc |= __opcode_to_mem_arm(offset);
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break;
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case R_ARM_V4BX:
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@ -121,8 +125,8 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
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* other bits to re-code instruction as
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* MOV PC,Rm.
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*/
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*(u32 *)loc &= 0xf000000f;
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*(u32 *)loc |= 0x01a0f000;
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*(u32 *)loc &= __opcode_to_mem_arm(0xf000000f);
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*(u32 *)loc |= __opcode_to_mem_arm(0x01a0f000);
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break;
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case R_ARM_PREL31:
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@ -132,7 +136,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
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case R_ARM_MOVW_ABS_NC:
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case R_ARM_MOVT_ABS:
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offset = *(u32 *)loc;
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offset = tmp = __mem_to_opcode_arm(*(u32 *)loc);
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offset = ((offset & 0xf0000) >> 4) | (offset & 0xfff);
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offset = (offset ^ 0x8000) - 0x8000;
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@ -140,16 +144,18 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
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if (ELF32_R_TYPE(rel->r_info) == R_ARM_MOVT_ABS)
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offset >>= 16;
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*(u32 *)loc &= 0xfff0f000;
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*(u32 *)loc |= ((offset & 0xf000) << 4) |
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(offset & 0x0fff);
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tmp &= 0xfff0f000;
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tmp |= ((offset & 0xf000) << 4) |
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(offset & 0x0fff);
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*(u32 *)loc = __opcode_to_mem_arm(tmp);
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break;
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#ifdef CONFIG_THUMB2_KERNEL
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case R_ARM_THM_CALL:
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case R_ARM_THM_JUMP24:
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upper = *(u16 *)loc;
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lower = *(u16 *)(loc + 2);
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upper = __mem_to_opcode_thumb16(*(u16 *)loc);
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lower = __mem_to_opcode_thumb16(*(u16 *)(loc + 2));
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/*
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* 25 bit signed address range (Thumb-2 BL and B.W
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@ -198,17 +204,20 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
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sign = (offset >> 24) & 1;
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j1 = sign ^ (~(offset >> 23) & 1);
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j2 = sign ^ (~(offset >> 22) & 1);
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*(u16 *)loc = (u16)((upper & 0xf800) | (sign << 10) |
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upper = (u16)((upper & 0xf800) | (sign << 10) |
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((offset >> 12) & 0x03ff));
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*(u16 *)(loc + 2) = (u16)((lower & 0xd000) |
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(j1 << 13) | (j2 << 11) |
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((offset >> 1) & 0x07ff));
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lower = (u16)((lower & 0xd000) |
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(j1 << 13) | (j2 << 11) |
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((offset >> 1) & 0x07ff));
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*(u16 *)loc = __opcode_to_mem_thumb16(upper);
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*(u16 *)(loc + 2) = __opcode_to_mem_thumb16(lower);
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break;
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case R_ARM_THM_MOVW_ABS_NC:
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case R_ARM_THM_MOVT_ABS:
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upper = *(u16 *)loc;
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lower = *(u16 *)(loc + 2);
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upper = __mem_to_opcode_thumb16(*(u16 *)loc);
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lower = __mem_to_opcode_thumb16(*(u16 *)(loc + 2));
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/*
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* MOVT/MOVW instructions encoding in Thumb-2:
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@ -229,12 +238,14 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
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if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_ABS)
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offset >>= 16;
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*(u16 *)loc = (u16)((upper & 0xfbf0) |
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((offset & 0xf000) >> 12) |
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((offset & 0x0800) >> 1));
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*(u16 *)(loc + 2) = (u16)((lower & 0x8f00) |
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((offset & 0x0700) << 4) |
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(offset & 0x00ff));
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upper = (u16)((upper & 0xfbf0) |
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((offset & 0xf000) >> 12) |
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((offset & 0x0800) >> 1));
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lower = (u16)((lower & 0x8f00) |
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((offset & 0x0700) << 4) |
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(offset & 0x00ff));
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*(u16 *)loc = __opcode_to_mem_thumb16(upper);
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*(u16 *)(loc + 2) = __opcode_to_mem_thumb16(lower);
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break;
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#endif
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