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Code

drm/nouveau: use pr_cont

Browse Source 
Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Marcin Slusarz 2012-12-09 15:45:20 +01:00 committed by Ben Skeggs
parent fc10199ee3
commit f533da1027
16 changed files with 53 additions and 53 deletions
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8
drivers/gpu/drm/nouveau/core/core/enum.c
View File

@ -45,9 +45,9 @@ nouveau_enum_print(const struct nouveau_enum *en, u32 value)
{
en = nouveau_enum_find(en, value);
if (en)
printk("%s", en->name);
pr_cont("%s", en->name);
else
printk("(unknown enum 0x%08x)", value);
pr_cont("(unknown enum 0x%08x)", value);
}
void
@ -55,7 +55,7 @@ nouveau_bitfield_print(const struct nouveau_bitfield *bf, u32 value)
{
while (bf->name) {
if (value & bf->mask) {
printk(" %s", bf->name);
pr_cont(" %s", bf->name);
value &= ~bf->mask;
}
@ -63,5 +63,5 @@ nouveau_bitfield_print(const struct nouveau_bitfield *bf, u32 value)
}
if (value)
printk(" (unknown bits 0x%08x)", value);
pr_cont(" (unknown bits 0x%08x)", value);
}

2
drivers/gpu/drm/nouveau/core/engine/copy/nva3.c
View File

@ -100,7 +100,7 @@ nva3_copy_intr(struct nouveau_subdev *subdev)
if (stat & 0x00000040) {
nv_error(falcon, "DISPATCH_ERROR [");
nouveau_enum_print(nva3_copy_isr_error_name, ssta);
printk("] ch %d [0x%010llx] subc %d mthd 0x%04x data 0x%08x\n",
pr_cont("] ch %d [0x%010llx] subc %d mthd 0x%04x data 0x%08x\n",
chid, inst << 12, subc, mthd, data);
nv_wo32(falcon, 0x004, 0x00000040);
stat &= ~0x00000040;

2
drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c
View File

@ -128,7 +128,7 @@ nv84_crypt_intr(struct nouveau_subdev *subdev)
if (stat) {
nv_error(priv, "");
nouveau_bitfield_print(nv84_crypt_intr_mask, stat);
printk(" ch %d [0x%010llx] mthd 0x%04x data 0x%08x\n",
pr_cont(" ch %d [0x%010llx] mthd 0x%04x data 0x%08x\n",
chid, (u64)inst << 12, mthd, data);
}

2
drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c
View File

@ -102,7 +102,7 @@ nv98_crypt_intr(struct nouveau_subdev *subdev)
if (stat & 0x00000040) {
nv_error(priv, "DISPATCH_ERROR [");
nouveau_enum_print(nv98_crypt_isr_error_name, ssta);
printk("] ch %d [0x%010llx] subc %d mthd 0x%04x data 0x%08x\n",
pr_cont("] ch %d [0x%010llx] subc %d mthd 0x%04x data 0x%08x\n",
chid, (u64)inst << 12, subc, mthd, data);
nv_wr32(priv, 0x087004, 0x00000040);
stat &= ~0x00000040;

10
drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
View File

@ -420,16 +420,16 @@ nvc0_fifo_isr_vm_fault(struct nvc0_fifo_priv *priv, int unit)
nv_error(priv, "%s fault at 0x%010llx [", (stat & 0x00000080) ?
"write" : "read", (u64)vahi << 32 | valo);
nouveau_enum_print(nvc0_fifo_fault_reason, stat & 0x0000000f);
printk("] from ");
pr_cont("] from ");
nouveau_enum_print(nvc0_fifo_fault_unit, unit);
if (stat & 0x00000040) {
printk("/");
pr_cont("/");
nouveau_enum_print(nvc0_fifo_fault_hubclient, client);
} else {
printk("/GPC%d/", (stat & 0x1f000000) >> 24);
pr_cont("/GPC%d/", (stat & 0x1f000000) >> 24);
nouveau_enum_print(nvc0_fifo_fault_gpcclient, client);
}
printk(" on channel 0x%010llx\n", (u64)inst << 12);
pr_cont(" on channel 0x%010llx\n", (u64)inst << 12);
}
static int
@ -484,7 +484,7 @@ nvc0_fifo_isr_subfifo_intr(struct nvc0_fifo_priv *priv, int unit)
if (show) {
nv_error(priv, "SUBFIFO%d:", unit);
nouveau_bitfield_print(nvc0_fifo_subfifo_intr, show);
printk("\n");
pr_cont("\n");
nv_error(priv, "SUBFIFO%d: ch %d subc %d mthd 0x%04x "
"data 0x%08x\n",
unit, chid, subc, mthd, data);

10
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
View File

@ -416,16 +416,16 @@ nve0_fifo_isr_vm_fault(struct nve0_fifo_priv *priv, int unit)
nv_error(priv, "PFIFO: %s fault at 0x%010llx [", (stat & 0x00000080) ?
"write" : "read", (u64)vahi << 32 | valo);
nouveau_enum_print(nve0_fifo_fault_reason, stat & 0x0000000f);
printk("] from ");
pr_cont("] from ");
nouveau_enum_print(nve0_fifo_fault_unit, unit);
if (stat & 0x00000040) {
printk("/");
pr_cont("/");
nouveau_enum_print(nve0_fifo_fault_hubclient, client);
} else {
printk("/GPC%d/", (stat & 0x1f000000) >> 24);
pr_cont("/GPC%d/", (stat & 0x1f000000) >> 24);
nouveau_enum_print(nve0_fifo_fault_gpcclient, client);
}
printk(" on channel 0x%010llx\n", (u64)inst << 12);
pr_cont(" on channel 0x%010llx\n", (u64)inst << 12);
}
static int
@ -480,7 +480,7 @@ nve0_fifo_isr_subfifo_intr(struct nve0_fifo_priv *priv, int unit)
if (show) {
nv_error(priv, "SUBFIFO%d:", unit);
nouveau_bitfield_print(nve0_fifo_subfifo_intr, show);
printk("\n");
pr_cont("\n");
nv_error(priv, "SUBFIFO%d: ch %d subc %d mthd 0x%04x "
"data 0x%08x\n",
unit, chid, subc, mthd, data);

6
drivers/gpu/drm/nouveau/core/engine/graph/nv04.c
View File

@ -1299,11 +1299,11 @@ nv04_graph_intr(struct nouveau_subdev *subdev)
if (show) {
nv_error(priv, "");
nouveau_bitfield_print(nv04_graph_intr_name, show);
printk(" nsource:");
pr_cont(" nsource:");
nouveau_bitfield_print(nv04_graph_nsource, nsource);
printk(" nstatus:");
pr_cont(" nstatus:");
nouveau_bitfield_print(nv04_graph_nstatus, nstatus);
printk("\n");
pr_cont("\n");
nv_error(priv, "ch %d/%d class 0x%04x "
"mthd 0x%04x data 0x%08x\n",
chid, subc, class, mthd, data);

6
drivers/gpu/drm/nouveau/core/engine/graph/nv10.c
View File

@ -1195,11 +1195,11 @@ nv10_graph_intr(struct nouveau_subdev *subdev)
if (show) {
nv_error(priv, "");
nouveau_bitfield_print(nv10_graph_intr_name, show);
printk(" nsource:");
pr_cont(" nsource:");
nouveau_bitfield_print(nv04_graph_nsource, nsource);
printk(" nstatus:");
pr_cont(" nstatus:");
nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
printk("\n");
pr_cont("\n");
nv_error(priv, "ch %d/%d class 0x%04x "
"mthd 0x%04x data 0x%08x\n",
chid, subc, class, mthd, data);

6
drivers/gpu/drm/nouveau/core/engine/graph/nv20.c
View File

@ -226,11 +226,11 @@ nv20_graph_intr(struct nouveau_subdev *subdev)
if (show) {
nv_error(priv, "");
nouveau_bitfield_print(nv10_graph_intr_name, show);
printk(" nsource:");
pr_cont(" nsource:");
nouveau_bitfield_print(nv04_graph_nsource, nsource);
printk(" nstatus:");
pr_cont(" nstatus:");
nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
printk("\n");
pr_cont("\n");
nv_error(priv, "ch %d/%d class 0x%04x mthd 0x%04x data 0x%08x\n",
chid, subc, class, mthd, data);
}

6
drivers/gpu/drm/nouveau/core/engine/graph/nv40.c
View File

@ -323,11 +323,11 @@ nv40_graph_intr(struct nouveau_subdev *subdev)
if (show) {
nv_error(priv, "");
nouveau_bitfield_print(nv10_graph_intr_name, show);
printk(" nsource:");
pr_cont(" nsource:");
nouveau_bitfield_print(nv04_graph_nsource, nsource);
printk(" nstatus:");
pr_cont(" nstatus:");
nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
printk("\n");
pr_cont("\n");
nv_error(priv, "ch %d [0x%08x] subc %d class 0x%04x "
"mthd 0x%04x data 0x%08x\n",
chid, inst << 4, subc, class, mthd, data);

14
drivers/gpu/drm/nouveau/core/engine/graph/nv50.c
View File

@ -418,7 +418,7 @@ nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display)
nv_error(priv, "TRAP_MP_EXEC - "
"TP %d MP %d: ", tpid, i);
nouveau_enum_print(nv50_mp_exec_error_names, status);
printk(" at %06x warp %d, opcode %08x %08x\n",
pr_cont(" at %06x warp %d, opcode %08x %08x\n",
pc&0xffffff, pc >> 24,
oplow, ophigh);
}
@ -623,7 +623,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
if (display) {
nv_error(priv, "TRAP_M2MF");
nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
printk("\n");
pr_cont("\n");
nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n",
nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808),
nv_rd32(priv, 0x40680c), nv_rd32(priv, 0x406810));
@ -644,7 +644,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
if (display) {
nv_error(priv, "TRAP_VFETCH");
nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
printk("\n");
pr_cont("\n");
nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n",
nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08),
nv_rd32(priv, 0x400c0c), nv_rd32(priv, 0x400c10));
@ -661,7 +661,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
if (display) {
nv_error(priv, "TRAP_STRMOUT");
nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
printk("\n");
pr_cont("\n");
nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n",
nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808),
nv_rd32(priv, 0x40180c), nv_rd32(priv, 0x401810));
@ -682,7 +682,7 @@ nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display,
if (display) {
nv_error(priv, "TRAP_CCACHE");
nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
printk("\n");
pr_cont("\n");
nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x"
" %08x %08x %08x\n",
nv_rd32(priv, 0x405000), nv_rd32(priv, 0x405004),
@ -774,7 +774,7 @@ nv50_graph_intr(struct nouveau_subdev *subdev)
u32 ecode = nv_rd32(priv, 0x400110);
nv_error(priv, "DATA_ERROR ");
nouveau_enum_print(nv50_data_error_names, ecode);
printk("\n");
pr_cont("\n");
}
if (stat & 0x00200000) {
@ -788,7 +788,7 @@ nv50_graph_intr(struct nouveau_subdev *subdev)
if (show) {
nv_error(priv, "");
nouveau_bitfield_print(nv50_graph_intr_name, show);
printk("\n");
pr_cont("\n");
nv_error(priv, "ch %d [0x%010llx] subc %d class 0x%04x "
"mthd 0x%04x data 0x%08x\n",
chid, (u64)inst << 12, subc, class, mthd, data);

2
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
View File

@ -454,7 +454,7 @@ nvc0_graph_intr(struct nouveau_subdev *subdev)
if (stat & 0x00100000) {
nv_error(priv, "DATA_ERROR [");
nouveau_enum_print(nv50_data_error_names, code);
printk("] ch %d [0x%010llx] subc %d class 0x%04x "
pr_cont("] ch %d [0x%010llx] subc %d class 0x%04x "
"mthd 0x%04x data 0x%08x\n",
chid, inst << 12, subc, class, mthd, data);
nv_wr32(priv, 0x400100, 0x00100000);

2
drivers/gpu/drm/nouveau/core/engine/graph/nve0.c
View File

@ -166,7 +166,7 @@ nve0_graph_intr(struct nouveau_subdev *subdev)
if (stat & 0x00100000) {
nv_error(priv, "DATA_ERROR [");
nouveau_enum_print(nv50_data_error_names, code);
printk("] ch %d [0x%010llx] subc %d class 0x%04x "
pr_cont("] ch %d [0x%010llx] subc %d class 0x%04x "
"mthd 0x%04x data 0x%08x\n",
chid, inst, subc, class, mthd, data);
nv_wr32(priv, 0x400100, 0x00100000);

18
drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
View File

@ -372,30 +372,30 @@ nv50_fb_intr(struct nouveau_subdev *subdev)
en = nouveau_enum_find(vm_engine, st0);
if (en)
printk("%s/", en->name);
pr_cont("%s/", en->name);
else
printk("%02x/", st0);
pr_cont("%02x/", st0);
cl = nouveau_enum_find(vm_client, st2);
if (cl)
printk("%s/", cl->name);
pr_cont("%s/", cl->name);
else
printk("%02x/", st2);
pr_cont("%02x/", st2);
if (cl && cl->data) cl = nouveau_enum_find(cl->data, st3);
else if (en && en->data) cl = nouveau_enum_find(en->data, st3);
else cl = NULL;
if (cl)
printk("%s", cl->name);
pr_cont("%s", cl->name);
else
printk("%02x", st3);
pr_cont("%02x", st3);
printk(" reason: ");
pr_cont(" reason: ");
en = nouveau_enum_find(vm_fault, st1);
if (en)
printk("%s\n", en->name);
pr_cont("%s\n", en->name);
else
printk("0x%08x\n", st1);
pr_cont("0x%08x\n", st1);
}
static int

8
drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.c
View File

@ -156,15 +156,15 @@ mxms_foreach(struct nouveau_mxm *mxm, u8 types,
nv_debug(mxm, "%4s: ", mxms_desc_name[type]);
for (j = headerlen - 1; j >= 0; j--)
printk("%02x", dump[j]);
printk("\n");
pr_cont("%02x", dump[j]);
pr_cont("\n");
dump += headerlen;
for (i = 0; i < entries; i++, dump += recordlen) {
nv_debug(mxm, " ");
for (j = recordlen - 1; j >= 0; j--)
printk("%02x", dump[j]);
printk("\n");
pr_cont("%02x", dump[j]);
pr_cont("\n");
}
}

4
drivers/gpu/drm/nouveau/nouveau_bios.c
View File

@ -1884,9 +1884,9 @@ parse_dcb_table(struct drm_device *dev, struct nvbios *bios)
if (conn[0] != 0xff) {
NV_INFO(drm, "DCB conn %02d: ", idx);
if (olddcb_conntab(dev)[3] < 4)
printk("%04x\n", ROM16(conn[0]));
pr_cont("%04x\n", ROM16(conn[0]));
else
printk("%08x\n", ROM32(conn[0]));
pr_cont("%08x\n", ROM32(conn[0]));
}
}
dcb_fake_connectors(bios);