mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-23 04:34:11 +08:00
Merge remote-tracking branch 'spi/topic/s3c64xx' into spi-next
This commit is contained in:
Mark Brown
commit
f4e975814e
@ -39,6 +39,7 @@
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#endif
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#define MAX_SPI_PORTS 3
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#define S3C64XX_SPI_QUIRK_POLL (1 << 0)
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/* Registers and bit-fields */
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@ -130,6 +131,7 @@
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#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
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#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
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#define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
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#define RXBUSY (1<<2)
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#define TXBUSY (1<<3)
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@ -158,6 +160,7 @@ struct s3c64xx_spi_port_config {
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int fifo_lvl_mask[MAX_SPI_PORTS];
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int rx_lvl_offset;
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int tx_st_done;
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int quirks;
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bool high_speed;
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bool clk_from_cmu;
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};
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@ -205,6 +208,7 @@ struct s3c64xx_spi_driver_data {
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struct s3c64xx_spi_port_config *port_conf;
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unsigned int port_id;
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unsigned long gpios[4];
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bool cs_gpio;
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};
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static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
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@ -344,8 +348,12 @@ static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
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{
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struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
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/* Acquire DMA channels */
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while (!acquire_dma(sdd))
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/*
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* If DMA resource was not available during
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* probe, no need to continue with dma requests
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* else Acquire DMA channels
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*/
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while (!is_polling(sdd) && !acquire_dma(sdd))
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usleep_range(10000, 11000);
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pm_runtime_get_sync(&sdd->pdev->dev);
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@ -358,9 +366,12 @@ static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
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struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
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/* Free DMA channels */
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sdd->ops->release((enum dma_ch)sdd->rx_dma.ch, &s3c64xx_spi_dma_client);
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sdd->ops->release((enum dma_ch)sdd->tx_dma.ch, &s3c64xx_spi_dma_client);
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if (!is_polling(sdd)) {
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sdd->ops->release((enum dma_ch)sdd->rx_dma.ch,
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&s3c64xx_spi_dma_client);
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sdd->ops->release((enum dma_ch)sdd->tx_dma.ch,
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&s3c64xx_spi_dma_client);
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}
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pm_runtime_put(&sdd->pdev->dev);
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return 0;
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@ -464,8 +475,10 @@ static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
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struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
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/* Free DMA channels */
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dma_release_channel(sdd->rx_dma.ch);
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dma_release_channel(sdd->tx_dma.ch);
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if (!is_polling(sdd)) {
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dma_release_channel(sdd->rx_dma.ch);
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dma_release_channel(sdd->tx_dma.ch);
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}
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pm_runtime_put(&sdd->pdev->dev);
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return 0;
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@ -558,14 +571,40 @@ static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
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if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
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/* Deselect the last toggled device */
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cs = sdd->tgl_spi->controller_data;
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gpio_set_value(cs->line,
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spi->mode & SPI_CS_HIGH ? 0 : 1);
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if (sdd->cs_gpio)
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gpio_set_value(cs->line,
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spi->mode & SPI_CS_HIGH ? 0 : 1);
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}
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sdd->tgl_spi = NULL;
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}
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cs = spi->controller_data;
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gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
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if (sdd->cs_gpio)
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gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0);
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/* Start the signals */
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writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
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}
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static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
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int timeout_ms)
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{
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void __iomem *regs = sdd->regs;
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unsigned long val = 1;
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u32 status;
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/* max fifo depth available */
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u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
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if (timeout_ms)
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val = msecs_to_loops(timeout_ms);
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do {
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status = readl(regs + S3C64XX_SPI_STATUS);
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} while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
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/* return the actual received data length */
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return RX_FIFO_LVL(status, sdd);
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}
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static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
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@ -590,20 +629,19 @@ static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
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} while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
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}
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if (!val)
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return -EIO;
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if (dma_mode) {
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u32 status;
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/*
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* If the previous xfer was completed within timeout, then
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* proceed further else return -EIO.
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* DmaTx returns after simply writing data in the FIFO,
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* w/o waiting for real transmission on the bus to finish.
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* DmaRx returns only after Dma read data from FIFO which
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* needs bus transmission to finish, so we don't worry if
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* Xfer involved Rx(with or without Tx).
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*/
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if (xfer->rx_buf == NULL) {
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if (val && !xfer->rx_buf) {
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val = msecs_to_loops(10);
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status = readl(regs + S3C64XX_SPI_STATUS);
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while ((TX_FIFO_LVL(status, sdd)
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@ -613,30 +651,54 @@ static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
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status = readl(regs + S3C64XX_SPI_STATUS);
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}
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if (!val)
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return -EIO;
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}
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/* If timed out while checking rx/tx status return error */
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if (!val)
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return -EIO;
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} else {
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int loops;
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u32 cpy_len;
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u8 *buf;
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/* If it was only Tx */
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if (xfer->rx_buf == NULL) {
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if (!xfer->rx_buf) {
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sdd->state &= ~TXBUSY;
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return 0;
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}
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switch (sdd->cur_bpw) {
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case 32:
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ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
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xfer->rx_buf, xfer->len / 4);
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break;
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case 16:
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ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
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xfer->rx_buf, xfer->len / 2);
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break;
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default:
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ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
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xfer->rx_buf, xfer->len);
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break;
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}
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/*
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* If the receive length is bigger than the controller fifo
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* size, calculate the loops and read the fifo as many times.
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* loops = length / max fifo size (calculated by using the
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* fifo mask).
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* For any size less than the fifo size the below code is
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* executed atleast once.
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*/
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loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
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buf = xfer->rx_buf;
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do {
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/* wait for data to be received in the fifo */
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cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
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(loops ? ms : 0));
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switch (sdd->cur_bpw) {
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case 32:
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ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
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buf, cpy_len / 4);
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break;
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case 16:
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ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
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buf, cpy_len / 2);
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break;
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default:
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ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
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buf, cpy_len);
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break;
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}
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buf = buf + cpy_len;
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} while (loops--);
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sdd->state &= ~RXBUSY;
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}
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@ -651,7 +713,11 @@ static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
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if (sdd->tgl_spi == spi)
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sdd->tgl_spi = NULL;
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gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
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if (sdd->cs_gpio)
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gpio_set_value(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1);
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/* Quiese the signals */
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writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
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}
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static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
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@ -733,7 +799,7 @@ static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
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struct device *dev = &sdd->pdev->dev;
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struct spi_transfer *xfer;
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if (msg->is_dma_mapped)
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if (is_polling(sdd) || msg->is_dma_mapped)
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return 0;
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/* First mark all xfer unmapped */
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@ -782,7 +848,7 @@ static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
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struct device *dev = &sdd->pdev->dev;
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struct spi_transfer *xfer;
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if (msg->is_dma_mapped)
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if (is_polling(sdd) || msg->is_dma_mapped)
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return;
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list_for_each_entry(xfer, &msg->transfers, transfer_list) {
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@ -861,8 +927,9 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
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/* Polling method for xfers not bigger than FIFO capacity */
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use_dma = 0;
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if (sdd->rx_dma.ch && sdd->tx_dma.ch &&
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(xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1)))
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if (!is_polling(sdd) &&
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(sdd->rx_dma.ch && sdd->tx_dma.ch &&
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(xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
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use_dma = 1;
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spin_lock_irqsave(&sdd->lock, flags);
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@ -876,17 +943,10 @@ static int s3c64xx_spi_transfer_one_message(struct spi_master *master,
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/* Slave Select */
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enable_cs(sdd, spi);
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/* Start the signals */
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writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
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spin_unlock_irqrestore(&sdd->lock, flags);
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status = wait_for_xfer(sdd, xfer, use_dma);
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/* Quiese the signals */
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writel(S3C64XX_SPI_SLAVE_SIG_INACT,
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sdd->regs + S3C64XX_SPI_SLAVE_SEL);
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if (status) {
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dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
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xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
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@ -942,8 +1002,10 @@ static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
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{
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struct s3c64xx_spi_csinfo *cs;
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struct device_node *slave_np, *data_np = NULL;
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struct s3c64xx_spi_driver_data *sdd;
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u32 fb_delay = 0;
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sdd = spi_master_get_devdata(spi->master);
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slave_np = spi->dev.of_node;
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if (!slave_np) {
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dev_err(&spi->dev, "device node not found\n");
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@ -963,7 +1025,10 @@ static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
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return ERR_PTR(-ENOMEM);
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}
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cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
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/* The CS line is asserted/deasserted by the gpio pin */
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if (sdd->cs_gpio)
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cs->line = of_get_named_gpio(data_np, "cs-gpio", 0);
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if (!gpio_is_valid(cs->line)) {
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dev_err(&spi->dev, "chip select gpio is not specified or invalid\n");
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kfree(cs);
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@ -1003,7 +1068,8 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
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return -ENODEV;
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}
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if (!spi_get_ctldata(spi)) {
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/* Request gpio only if cs line is asserted by gpio pins */
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if (sdd->cs_gpio) {
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err = gpio_request_one(cs->line, GPIOF_OUT_INIT_HIGH,
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dev_name(&spi->dev));
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if (err) {
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@ -1012,9 +1078,11 @@ static int s3c64xx_spi_setup(struct spi_device *spi)
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cs->line, err);
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goto err_gpio_req;
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}
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spi_set_ctldata(spi, cs);
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}
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if (!spi_get_ctldata(spi))
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spi_set_ctldata(spi, cs);
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sci = sdd->cntrlr_info;
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spin_lock_irqsave(&sdd->lock, flags);
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@ -1092,8 +1160,10 @@ err_gpio_req:
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static void s3c64xx_spi_cleanup(struct spi_device *spi)
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{
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struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
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struct s3c64xx_spi_driver_data *sdd;
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if (cs) {
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sdd = spi_master_get_devdata(spi->master);
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if (cs && sdd->cs_gpio) {
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gpio_free(cs->line);
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if (spi->dev.of_node)
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kfree(cs);
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@ -1270,7 +1340,11 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
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sdd->cntrlr_info = sci;
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sdd->pdev = pdev;
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sdd->sfr_start = mem_res->start;
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sdd->cs_gpio = true;
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if (pdev->dev.of_node) {
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if (!of_find_property(pdev->dev.of_node, "cs-gpio", NULL))
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sdd->cs_gpio = false;
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ret = of_alias_get_id(pdev->dev.of_node, "spi");
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
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@ -1287,19 +1361,19 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
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if (!sdd->pdev->dev.of_node) {
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res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
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if (!res) {
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dev_err(&pdev->dev, "Unable to get SPI tx dma "
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"resource\n");
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return -ENXIO;
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}
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sdd->tx_dma.dmach = res->start;
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dev_warn(&pdev->dev, "Unable to get SPI tx dma "
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"resource. Switching to poll mode\n");
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sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
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} else
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sdd->tx_dma.dmach = res->start;
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res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
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if (!res) {
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dev_err(&pdev->dev, "Unable to get SPI rx dma "
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"resource\n");
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return -ENXIO;
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}
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sdd->rx_dma.dmach = res->start;
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dev_warn(&pdev->dev, "Unable to get SPI rx dma "
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"resource. Switching to poll mode\n");
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sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
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} else
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sdd->rx_dma.dmach = res->start;
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}
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sdd->tx_dma.direction = DMA_MEM_TO_DEV;
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@ -1534,6 +1608,15 @@ static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
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.clk_from_cmu = true,
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};
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static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
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.fifo_lvl_mask = { 0x1ff },
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.rx_lvl_offset = 15,
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.tx_st_done = 25,
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.high_speed = true,
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.clk_from_cmu = true,
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.quirks = S3C64XX_SPI_QUIRK_POLL,
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};
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static struct platform_device_id s3c64xx_spi_driver_ids[] = {
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{
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.name = "s3c2443-spi",
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@ -1557,15 +1640,16 @@ static struct platform_device_id s3c64xx_spi_driver_ids[] = {
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{ },
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};
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#ifdef CONFIG_OF
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static const struct of_device_id s3c64xx_spi_dt_match[] = {
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{ .compatible = "samsung,exynos4210-spi",
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.data = (void *)&exynos4_spi_port_config,
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},
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{ .compatible = "samsung,exynos5440-spi",
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.data = (void *)&exynos5440_spi_port_config,
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},
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{ },
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};
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MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
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#endif /* CONFIG_OF */
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static struct platform_driver s3c64xx_spi_driver = {
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.driver = {
|
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|
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