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perf/x86/intel/cqm: Document PQR MSR abuse

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The CQM code acts like it owns the PQR MSR completely. That's not true
because only the lower 10 bits are used for CQM. The upper 32 bits are
used for the 'CLass Of Service ID' (CLOSID). Document the abuse. Will be
fixed in a later patch.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Matt Fleming <matt.fleming@intel.com>
Cc: Kanaka Juvva <kanaka.d.juvva@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Vikas Shivappa <vikas.shivappa@linux.intel.com>
Cc: Will Auld <will.auld@intel.com>
Link: http://lkml.kernel.org/r/20150518235149.823214798@linutronix.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Thomas Gleixner 2015-05-19 00:00:50 +00:00 committed by Ingo Molnar
parent 8d12ded3dd
commit f4d9757ca6
1 changed files with 13 additions and 2 deletions
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15
arch/x86/kernel/cpu/perf_event_intel_cqm.c
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@ -978,7 +978,12 @@ static void intel_cqm_event_start(struct perf_event *event, int mode)
WARN_ON_ONCE(state->rmid); WARN_ON_ONCE(state->rmid);
state->rmid = rmid; state->rmid = rmid;
wrmsrl(MSR_IA32_PQR_ASSOC, state->rmid); /*
* This is actually wrong, as the upper 32 bit MSR contain the
* closid which is used for configuring the Cache Allocation
* Technology component.
*/
wrmsr(MSR_IA32_PQR_ASSOC, rmid, 0);
raw_spin_unlock_irqrestore(&state->lock, flags); raw_spin_unlock_irqrestore(&state->lock, flags);
} }
@ -998,7 +1003,13 @@ static void intel_cqm_event_stop(struct perf_event *event, int mode)
if (!--state->cnt) { if (!--state->cnt) {
state->rmid = 0; state->rmid = 0;
wrmsrl(MSR_IA32_PQR_ASSOC, 0); /*
* This is actually wrong, as the upper 32 bit of the
* MSR contain the closid which is used for
* configuring the Cache Allocation Technology
* component.
*/
wrmsr(MSR_IA32_PQR_ASSOC, 0, 0);
} else { } else {
WARN_ON_ONCE(!state->rmid); WARN_ON_ONCE(!state->rmid);
} }