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clk: qcom: clk-alpha-pll: Add support for Lucid 5LPE PLL
Lucid 5LPE is a slightly different Lucid PLL with different offsets and porgramming sequence so add support for these Signed-off-by: Vivek Aknurwar <viveka@codeaurora.org> Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org> [vkoul: rebase and tidy up for upstream] Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210127070811.152690-4-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -156,6 +156,12 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
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/* LUCID PLL specific settings and offsets */
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#define LUCID_PCAL_DONE BIT(27)
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/* LUCID 5LPE PLL specific settings and offsets */
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#define LUCID_5LPE_PCAL_DONE BIT(11)
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#define LUCID_5LPE_ALPHA_PLL_ACK_LATCH BIT(13)
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#define LUCID_5LPE_PLL_LATCH_INPUT BIT(14)
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#define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21)
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#define pll_alpha_width(p) \
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((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
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ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
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@ -1604,3 +1610,170 @@ const struct clk_ops clk_alpha_pll_agera_ops = {
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.set_rate = clk_alpha_pll_agera_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);
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static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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u32 val;
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int ret;
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ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
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if (ret)
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return ret;
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/* If in FSM mode, just vote for it */
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if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
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ret = clk_enable_regmap(hw);
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if (ret)
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return ret;
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return wait_for_pll_enable_lock(pll);
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}
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/* Check if PLL is already enabled, return if enabled */
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ret = trion_pll_is_enabled(pll, pll->clkr.regmap);
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if (ret < 0)
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return ret;
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ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
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if (ret)
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return ret;
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regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN);
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ret = wait_for_pll_enable_lock(pll);
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if (ret)
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return ret;
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/* Enable the PLL outputs */
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ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
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if (ret)
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return ret;
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/* Enable the global PLL outputs */
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return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
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}
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static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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u32 val;
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int ret;
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ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
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if (ret)
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return;
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/* If in FSM mode, just unvote it */
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if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
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clk_disable_regmap(hw);
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return;
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}
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/* Disable the global PLL output */
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ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
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if (ret)
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return;
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/* Disable the PLL outputs */
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ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
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if (ret)
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return;
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/* Place the PLL mode in STANDBY */
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regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY);
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}
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/*
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* The Lucid 5LPE PLL requires a power-on self-calibration which happens
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* when the PLL comes out of reset. Calibrate in case it is not completed.
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*/
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static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw)
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{
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struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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struct clk_hw *p;
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u32 val = 0;
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int ret;
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/* Return early if calibration is not needed. */
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regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
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if (val & LUCID_5LPE_PCAL_DONE)
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return 0;
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p = clk_hw_get_parent(hw);
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if (!p)
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return -EINVAL;
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ret = alpha_pll_lucid_5lpe_enable(hw);
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if (ret)
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return ret;
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alpha_pll_lucid_5lpe_disable(hw);
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return 0;
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}
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static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long prate)
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{
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return __alpha_pll_trion_set_rate(hw, rate, prate,
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LUCID_5LPE_PLL_LATCH_INPUT,
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LUCID_5LPE_ALPHA_PLL_ACK_LATCH);
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}
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static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
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int i, val = 0, div, ret;
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u32 mask;
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/*
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* If the PLL is in FSM mode, then treat set_rate callback as a
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* no-operation.
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*/
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ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
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if (ret)
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return ret;
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if (val & LUCID_5LPE_ENABLE_VOTE_RUN)
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return 0;
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div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
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for (i = 0; i < pll->num_post_div; i++) {
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if (pll->post_div_table[i].div == div) {
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val = pll->post_div_table[i].val;
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break;
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}
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}
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mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift);
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return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
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mask, val << pll->post_div_shift);
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}
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const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = {
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.prepare = alpha_pll_lucid_5lpe_prepare,
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.enable = alpha_pll_lucid_5lpe_enable,
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.disable = alpha_pll_lucid_5lpe_disable,
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.is_enabled = clk_trion_pll_is_enabled,
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.recalc_rate = clk_trion_pll_recalc_rate,
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.round_rate = clk_alpha_pll_round_rate,
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.set_rate = alpha_pll_lucid_5lpe_set_rate,
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};
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EXPORT_SYMBOL(clk_alpha_pll_lucid_5lpe_ops);
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const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = {
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.enable = alpha_pll_lucid_5lpe_enable,
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.disable = alpha_pll_lucid_5lpe_disable,
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.is_enabled = clk_trion_pll_is_enabled,
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.recalc_rate = clk_trion_pll_recalc_rate,
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.round_rate = clk_alpha_pll_round_rate,
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};
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EXPORT_SYMBOL(clk_alpha_pll_fixed_lucid_5lpe_ops);
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const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
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.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
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.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
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.set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
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};
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EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
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@ -144,6 +144,10 @@ extern const struct clk_ops clk_alpha_pll_lucid_ops;
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extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
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extern const struct clk_ops clk_alpha_pll_agera_ops;
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extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops;
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extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops;
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extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;
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void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config);
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void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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