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i2c: iproc: Add slave mode support
Add slave mode support to the iProc I2C driver. Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Signed-off-by: Michael Cheng <ccheng@broadcom.com> Signed-off-by: Shreesha Rajashekar <shreesha.rajashekar@broadcom.com> Signed-off-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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@ -447,6 +447,7 @@ config I2C_BCM_IPROC
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tristate "Broadcom iProc I2C controller"
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depends on ARCH_BCM_IPROC || COMPILE_TEST
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default ARCH_BCM_IPROC
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select I2C_SLAVE
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help
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If you say yes to this option, support will be included for the
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Broadcom iProc I2C controller.
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@ -23,11 +23,30 @@
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#define CFG_OFFSET 0x00
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#define CFG_RESET_SHIFT 31
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#define CFG_EN_SHIFT 30
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#define CFG_SLAVE_ADDR_0_SHIFT 28
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#define CFG_M_RETRY_CNT_SHIFT 16
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#define CFG_M_RETRY_CNT_MASK 0x0f
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#define TIM_CFG_OFFSET 0x04
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#define TIM_CFG_MODE_400_SHIFT 31
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#define TIM_RAND_SLAVE_STRETCH_SHIFT 24
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#define TIM_RAND_SLAVE_STRETCH_MASK 0x7f
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#define TIM_PERIODIC_SLAVE_STRETCH_SHIFT 16
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#define TIM_PERIODIC_SLAVE_STRETCH_MASK 0x7f
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#define S_CFG_SMBUS_ADDR_OFFSET 0x08
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#define S_CFG_EN_NIC_SMB_ADDR3_SHIFT 31
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#define S_CFG_NIC_SMB_ADDR3_SHIFT 24
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#define S_CFG_NIC_SMB_ADDR3_MASK 0x7f
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#define S_CFG_EN_NIC_SMB_ADDR2_SHIFT 23
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#define S_CFG_NIC_SMB_ADDR2_SHIFT 16
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#define S_CFG_NIC_SMB_ADDR2_MASK 0x7f
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#define S_CFG_EN_NIC_SMB_ADDR1_SHIFT 15
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#define S_CFG_NIC_SMB_ADDR1_SHIFT 8
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#define S_CFG_NIC_SMB_ADDR1_MASK 0x7f
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#define S_CFG_EN_NIC_SMB_ADDR0_SHIFT 7
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#define S_CFG_NIC_SMB_ADDR0_SHIFT 0
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#define S_CFG_NIC_SMB_ADDR0_MASK 0x7f
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#define M_FIFO_CTRL_OFFSET 0x0c
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#define M_FIFO_RX_FLUSH_SHIFT 31
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@ -37,6 +56,14 @@
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#define M_FIFO_RX_THLD_SHIFT 8
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#define M_FIFO_RX_THLD_MASK 0x3f
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#define S_FIFO_CTRL_OFFSET 0x10
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#define S_FIFO_RX_FLUSH_SHIFT 31
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#define S_FIFO_TX_FLUSH_SHIFT 30
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#define S_FIFO_RX_CNT_SHIFT 16
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#define S_FIFO_RX_CNT_MASK 0x7f
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#define S_FIFO_RX_THLD_SHIFT 8
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#define S_FIFO_RX_THLD_MASK 0x3f
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#define M_CMD_OFFSET 0x30
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#define M_CMD_START_BUSY_SHIFT 31
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#define M_CMD_STATUS_SHIFT 25
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@ -54,17 +81,36 @@
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#define M_CMD_RD_CNT_SHIFT 0
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#define M_CMD_RD_CNT_MASK 0xff
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#define S_CMD_OFFSET 0x34
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#define S_CMD_START_BUSY_SHIFT 31
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#define S_CMD_STATUS_SHIFT 23
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#define S_CMD_STATUS_MASK 0x07
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#define S_CMD_STATUS_SUCCESS 0x0
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#define S_CMD_STATUS_TIMEOUT 0x5
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#define IE_OFFSET 0x38
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#define IE_M_RX_FIFO_FULL_SHIFT 31
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#define IE_M_RX_THLD_SHIFT 30
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#define IE_M_START_BUSY_SHIFT 28
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#define IE_M_TX_UNDERRUN_SHIFT 27
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#define IE_S_RX_FIFO_FULL_SHIFT 26
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#define IE_S_RX_THLD_SHIFT 25
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#define IE_S_RX_EVENT_SHIFT 24
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#define IE_S_START_BUSY_SHIFT 23
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#define IE_S_TX_UNDERRUN_SHIFT 22
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#define IE_S_RD_EVENT_SHIFT 21
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#define IS_OFFSET 0x3c
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#define IS_M_RX_FIFO_FULL_SHIFT 31
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#define IS_M_RX_THLD_SHIFT 30
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#define IS_M_START_BUSY_SHIFT 28
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#define IS_M_TX_UNDERRUN_SHIFT 27
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#define IS_S_RX_FIFO_FULL_SHIFT 26
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#define IS_S_RX_THLD_SHIFT 25
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#define IS_S_RX_EVENT_SHIFT 24
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#define IS_S_START_BUSY_SHIFT 23
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#define IS_S_TX_UNDERRUN_SHIFT 22
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#define IS_S_RD_EVENT_SHIFT 21
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#define M_TX_OFFSET 0x40
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#define M_TX_WR_STATUS_SHIFT 31
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@ -78,6 +124,18 @@
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#define M_RX_DATA_SHIFT 0
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#define M_RX_DATA_MASK 0xff
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#define S_TX_OFFSET 0x48
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#define S_TX_WR_STATUS_SHIFT 31
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#define S_TX_DATA_SHIFT 0
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#define S_TX_DATA_MASK 0xff
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#define S_RX_OFFSET 0x4c
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#define S_RX_STATUS_SHIFT 30
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#define S_RX_STATUS_MASK 0x03
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#define S_RX_PEC_ERR_SHIFT 29
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#define S_RX_DATA_SHIFT 0
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#define S_RX_DATA_MASK 0xff
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#define I2C_TIMEOUT_MSEC 50000
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#define M_TX_RX_FIFO_SIZE 64
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#define M_RX_FIFO_MAX_THLD_VALUE (M_TX_RX_FIFO_SIZE - 1)
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@ -85,6 +143,30 @@
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#define M_RX_MAX_READ_LEN 255
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#define M_RX_FIFO_THLD_VALUE 50
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#define IE_M_ALL_INTERRUPT_SHIFT 27
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#define IE_M_ALL_INTERRUPT_MASK 0x1e
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#define SLAVE_READ_WRITE_BIT_MASK 0x1
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#define SLAVE_READ_WRITE_BIT_SHIFT 0x1
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#define SLAVE_MAX_SIZE_TRANSACTION 64
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#define SLAVE_CLOCK_STRETCH_TIME 25
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#define IE_S_ALL_INTERRUPT_SHIFT 21
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#define IE_S_ALL_INTERRUPT_MASK 0x3f
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enum i2c_slave_read_status {
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I2C_SLAVE_RX_FIFO_EMPTY = 0,
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I2C_SLAVE_RX_START,
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I2C_SLAVE_RX_DATA,
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I2C_SLAVE_RX_END,
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};
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enum i2c_slave_xfer_dir {
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I2C_SLAVE_DIR_READ = 0,
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I2C_SLAVE_DIR_WRITE,
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I2C_SLAVE_DIR_NONE,
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};
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enum bus_speed_index {
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I2C_SPD_100K = 0,
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I2C_SPD_400K,
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@ -104,6 +186,9 @@ struct bcm_iproc_i2c_dev {
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struct i2c_msg *msg;
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struct i2c_client *slave;
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enum i2c_slave_xfer_dir xfer_dir;
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/* bytes that have been transferred */
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unsigned int tx_bytes;
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/* bytes that have been read */
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@ -117,6 +202,156 @@ struct bcm_iproc_i2c_dev {
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#define ISR_MASK (BIT(IS_M_START_BUSY_SHIFT) | BIT(IS_M_TX_UNDERRUN_SHIFT)\
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| BIT(IS_M_RX_THLD_SHIFT))
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#define ISR_MASK_SLAVE (BIT(IS_S_START_BUSY_SHIFT)\
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| BIT(IS_S_RX_EVENT_SHIFT) | BIT(IS_S_RD_EVENT_SHIFT))
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static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave);
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static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave);
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static void bcm_iproc_i2c_enable_disable(struct bcm_iproc_i2c_dev *iproc_i2c,
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bool enable);
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static void bcm_iproc_i2c_slave_init(
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struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset)
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{
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u32 val;
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if (need_reset) {
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/* put controller in reset */
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val = readl(iproc_i2c->base + CFG_OFFSET);
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val |= BIT(CFG_RESET_SHIFT);
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writel(val, iproc_i2c->base + CFG_OFFSET);
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/* wait 100 usec per spec */
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udelay(100);
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/* bring controller out of reset */
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val &= ~(BIT(CFG_RESET_SHIFT));
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writel(val, iproc_i2c->base + CFG_OFFSET);
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}
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/* flush TX/RX FIFOs */
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val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT));
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writel(val, iproc_i2c->base + S_FIFO_CTRL_OFFSET);
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/* Maximum slave stretch time */
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val = readl(iproc_i2c->base + TIM_CFG_OFFSET);
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val &= ~(TIM_RAND_SLAVE_STRETCH_MASK << TIM_RAND_SLAVE_STRETCH_SHIFT);
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val |= (SLAVE_CLOCK_STRETCH_TIME << TIM_RAND_SLAVE_STRETCH_SHIFT);
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writel(val, iproc_i2c->base + TIM_CFG_OFFSET);
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/* Configure the slave address */
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val = readl(iproc_i2c->base + S_CFG_SMBUS_ADDR_OFFSET);
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val |= BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
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val &= ~(S_CFG_NIC_SMB_ADDR3_MASK << S_CFG_NIC_SMB_ADDR3_SHIFT);
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val |= (iproc_i2c->slave->addr << S_CFG_NIC_SMB_ADDR3_SHIFT);
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writel(val, iproc_i2c->base + S_CFG_SMBUS_ADDR_OFFSET);
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/* clear all pending slave interrupts */
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writel(ISR_MASK_SLAVE, iproc_i2c->base + IS_OFFSET);
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/* Enable interrupt register for any READ event */
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val = BIT(IE_S_RD_EVENT_SHIFT);
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/* Enable interrupt register to indicate a valid byte in receive fifo */
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val |= BIT(IE_S_RX_EVENT_SHIFT);
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/* Enable interrupt register for the Slave BUSY command */
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val |= BIT(IE_S_START_BUSY_SHIFT);
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writel(val, iproc_i2c->base + IE_OFFSET);
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iproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE;
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}
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static void bcm_iproc_i2c_check_slave_status(
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struct bcm_iproc_i2c_dev *iproc_i2c)
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{
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u32 val;
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val = readl(iproc_i2c->base + S_CMD_OFFSET);
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val = (val >> S_CMD_STATUS_SHIFT) & S_CMD_STATUS_MASK;
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if (val == S_CMD_STATUS_TIMEOUT) {
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dev_err(iproc_i2c->device, "slave random stretch time timeout\n");
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/* re-initialize i2c for recovery */
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bcm_iproc_i2c_enable_disable(iproc_i2c, false);
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bcm_iproc_i2c_slave_init(iproc_i2c, true);
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bcm_iproc_i2c_enable_disable(iproc_i2c, true);
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}
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}
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static bool bcm_iproc_i2c_slave_isr(struct bcm_iproc_i2c_dev *iproc_i2c,
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u32 status)
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{
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u8 value;
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u32 val;
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u32 rd_status;
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u32 tmp;
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/* Start of transaction. check address and populate the direction */
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if (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_NONE) {
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tmp = readl(iproc_i2c->base + S_RX_OFFSET);
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rd_status = (tmp >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
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/* This condition checks whether the request is a new request */
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if (((rd_status == I2C_SLAVE_RX_START) &&
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(status & BIT(IS_S_RX_EVENT_SHIFT))) ||
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((rd_status == I2C_SLAVE_RX_END) &&
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(status & BIT(IS_S_RD_EVENT_SHIFT)))) {
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/* Last bit is W/R bit.
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* If 1 then its a read request(by master).
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*/
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iproc_i2c->xfer_dir = tmp & SLAVE_READ_WRITE_BIT_MASK;
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if (iproc_i2c->xfer_dir == I2C_SLAVE_DIR_WRITE)
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i2c_slave_event(iproc_i2c->slave,
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I2C_SLAVE_READ_REQUESTED, &value);
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else
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i2c_slave_event(iproc_i2c->slave,
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I2C_SLAVE_WRITE_REQUESTED, &value);
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}
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}
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/* read request from master */
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if ((status & BIT(IS_S_RD_EVENT_SHIFT)) &&
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(iproc_i2c->xfer_dir == I2C_SLAVE_DIR_WRITE)) {
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i2c_slave_event(iproc_i2c->slave,
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I2C_SLAVE_READ_PROCESSED, &value);
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writel(value, iproc_i2c->base + S_TX_OFFSET);
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val = BIT(S_CMD_START_BUSY_SHIFT);
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writel(val, iproc_i2c->base + S_CMD_OFFSET);
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}
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/* write request from master */
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if ((status & BIT(IS_S_RX_EVENT_SHIFT)) &&
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(iproc_i2c->xfer_dir == I2C_SLAVE_DIR_READ)) {
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val = readl(iproc_i2c->base + S_RX_OFFSET);
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/* Its a write request by Master to Slave.
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* We read data present in receive FIFO
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*/
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value = (u8)((val >> S_RX_DATA_SHIFT) & S_RX_DATA_MASK);
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i2c_slave_event(iproc_i2c->slave,
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I2C_SLAVE_WRITE_RECEIVED, &value);
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/* check the status for the last byte of the transaction */
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rd_status = (val >> S_RX_STATUS_SHIFT) & S_RX_STATUS_MASK;
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if (rd_status == I2C_SLAVE_RX_END)
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iproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE;
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dev_dbg(iproc_i2c->device, "\nread value = 0x%x\n", value);
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}
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/* Stop */
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if (status & BIT(IS_S_START_BUSY_SHIFT)) {
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i2c_slave_event(iproc_i2c->slave, I2C_SLAVE_STOP, &value);
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iproc_i2c->xfer_dir = I2C_SLAVE_DIR_NONE;
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}
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/* clear interrupt status */
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writel(status, iproc_i2c->base + IS_OFFSET);
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bcm_iproc_i2c_check_slave_status(iproc_i2c);
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return true;
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}
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static void bcm_iproc_i2c_read_valid_bytes(struct bcm_iproc_i2c_dev *iproc_i2c)
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{
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struct i2c_msg *msg = iproc_i2c->msg;
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@ -140,6 +375,18 @@ static irqreturn_t bcm_iproc_i2c_isr(int irq, void *data)
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u32 status = readl(iproc_i2c->base + IS_OFFSET);
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u32 tmp;
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bool ret;
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u32 sl_status = status & ISR_MASK_SLAVE;
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if (sl_status) {
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ret = bcm_iproc_i2c_slave_isr(iproc_i2c, sl_status);
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if (ret)
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return IRQ_HANDLED;
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else
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return IRQ_NONE;
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}
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status &= ISR_MASK;
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if (!status)
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@ -222,22 +469,25 @@ static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c)
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/* put controller in reset */
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val = readl(iproc_i2c->base + CFG_OFFSET);
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val |= 1 << CFG_RESET_SHIFT;
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val &= ~(1 << CFG_EN_SHIFT);
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val |= BIT(CFG_RESET_SHIFT);
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val &= ~(BIT(CFG_EN_SHIFT));
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writel(val, iproc_i2c->base + CFG_OFFSET);
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/* wait 100 usec per spec */
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udelay(100);
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/* bring controller out of reset */
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val &= ~(1 << CFG_RESET_SHIFT);
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val &= ~(BIT(CFG_RESET_SHIFT));
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writel(val, iproc_i2c->base + CFG_OFFSET);
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/* flush TX/RX FIFOs and set RX FIFO threshold to zero */
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val = (1 << M_FIFO_RX_FLUSH_SHIFT) | (1 << M_FIFO_TX_FLUSH_SHIFT);
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val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT));
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writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET);
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/* disable all interrupts */
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writel(0, iproc_i2c->base + IE_OFFSET);
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val = readl(iproc_i2c->base + IE_OFFSET);
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val &= ~(IE_M_ALL_INTERRUPT_MASK <<
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IE_M_ALL_INTERRUPT_SHIFT);
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writel(val, iproc_i2c->base + IE_OFFSET);
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/* clear all pending interrupts */
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writel(0xffffffff, iproc_i2c->base + IS_OFFSET);
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@ -440,12 +690,14 @@ static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter,
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static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap)
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{
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SLAVE;
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}
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static const struct i2c_algorithm bcm_iproc_algo = {
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.master_xfer = bcm_iproc_i2c_xfer,
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.functionality = bcm_iproc_i2c_functionality,
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.reg_slave = bcm_iproc_i2c_reg_slave,
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.unreg_slave = bcm_iproc_i2c_unreg_slave,
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};
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static struct i2c_adapter_quirks bcm_iproc_i2c_quirks = {
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@ -610,6 +862,46 @@ static const struct dev_pm_ops bcm_iproc_i2c_pm_ops = {
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#define BCM_IPROC_I2C_PM_OPS NULL
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#endif /* CONFIG_PM_SLEEP */
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static int bcm_iproc_i2c_reg_slave(struct i2c_client *slave)
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{
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struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
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if (iproc_i2c->slave)
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return -EBUSY;
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||||
|
||||
if (slave->flags & I2C_CLIENT_TEN)
|
||||
return -EAFNOSUPPORT;
|
||||
|
||||
iproc_i2c->slave = slave;
|
||||
bcm_iproc_i2c_slave_init(iproc_i2c, false);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bcm_iproc_i2c_unreg_slave(struct i2c_client *slave)
|
||||
{
|
||||
u32 tmp;
|
||||
struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(slave->adapter);
|
||||
|
||||
if (!iproc_i2c->slave)
|
||||
return -EINVAL;
|
||||
|
||||
iproc_i2c->slave = NULL;
|
||||
|
||||
/* disable all slave interrupts */
|
||||
tmp = readl(iproc_i2c->base + IE_OFFSET);
|
||||
tmp &= ~(IE_S_ALL_INTERRUPT_MASK <<
|
||||
IE_S_ALL_INTERRUPT_SHIFT);
|
||||
writel(tmp, iproc_i2c->base + IE_OFFSET);
|
||||
|
||||
/* Erase the slave address programmed */
|
||||
tmp = readl(iproc_i2c->base + S_CFG_SMBUS_ADDR_OFFSET);
|
||||
tmp &= ~BIT(S_CFG_EN_NIC_SMB_ADDR3_SHIFT);
|
||||
writel(tmp, iproc_i2c->base + S_CFG_SMBUS_ADDR_OFFSET);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id bcm_iproc_i2c_of_match[] = {
|
||||
{ .compatible = "brcm,iproc-i2c" },
|
||||
{ /* sentinel */ }
|
||||
|
Loading…
Reference in New Issue
Block a user