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scsi: lpfc: use dma_set_mask_and_coherent

The driver currently uses pci_set_dma_mask despite otherwise using the
generic DMA API.  Switch it over to the better generic DMA API.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Christoph Hellwig 2018-10-18 15:10:21 +02:00 committed by Martin K. Petersen
parent 52f603fee1
commit f30e1bfd61

View File

@ -7352,26 +7352,19 @@ lpfc_post_init_setup(struct lpfc_hba *phba)
static int
lpfc_sli_pci_mem_setup(struct lpfc_hba *phba)
{
struct pci_dev *pdev;
struct pci_dev *pdev = phba->pcidev;
unsigned long bar0map_len, bar2map_len;
int i, hbq_count;
void *ptr;
int error = -ENODEV;
/* Obtain PCI device reference */
if (!phba->pcidev)
if (!pdev)
return error;
else
pdev = phba->pcidev;
/* Set the device DMA mask size */
if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0
|| pci_set_consistent_dma_mask(pdev,DMA_BIT_MASK(64)) != 0) {
if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0
|| pci_set_consistent_dma_mask(pdev,DMA_BIT_MASK(32)) != 0) {
if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) ||
dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
return error;
}
}
/* Get the bus address of Bar0 and Bar2 and the number of bytes
* required by each mapping.
@ -9735,25 +9728,18 @@ out:
static int
lpfc_sli4_pci_mem_setup(struct lpfc_hba *phba)
{
struct pci_dev *pdev;
struct pci_dev *pdev = phba->pcidev;
unsigned long bar0map_len, bar1map_len, bar2map_len;
int error = -ENODEV;
uint32_t if_type;
/* Obtain PCI device reference */
if (!phba->pcidev)
if (!pdev)
return error;
else
pdev = phba->pcidev;
/* Set the device DMA mask size */
if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0
|| pci_set_consistent_dma_mask(pdev,DMA_BIT_MASK(64)) != 0) {
if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0
|| pci_set_consistent_dma_mask(pdev,DMA_BIT_MASK(32)) != 0) {
if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) ||
dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
return error;
}
}
/*
* The BARs and register set definitions and offset locations are