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https://github.com/edk2-porting/linux-next.git
synced 2024-12-25 05:34:00 +08:00
staging/rdma/hfi1: Fix for generic I2C interface
The original I2C interface was geared for QSFP accesses. Modify the interface to behave more like a generic I2C controller such that reads and writes can accept multi-byte offsets. Removed reads following writes and moved reset to top level. Reviewed-by: Easwar Hariharan <easwar.hariharan@intel.com> Reviewed-by: Dean Luick <dean.luick@intel.com> Signed-off-by: Pablo Cacho <pablo.cacho@intel.com> Signed-off-by: Jubin John <jubin.john@intel.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
This commit is contained in:
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89abfc8d64
commit
f1bf296340
@ -463,7 +463,8 @@ static ssize_t __i2c_debugfs_write(struct file *file, const char __user *buf,
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goto _free;
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}
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i2c_addr = (*ppos >> 16) & 0xff;
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/* byte offset format: [offsetSize][i2cAddr][offsetHigh][offsetLow] */
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i2c_addr = (*ppos >> 16) & 0xffff;
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offset = *ppos & 0xffff;
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total_written = i2c_write(ppd, target, i2c_addr, offset, buff, count);
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@ -517,7 +518,8 @@ static ssize_t __i2c_debugfs_read(struct file *file, char __user *buf,
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goto _return;
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}
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i2c_addr = (*ppos >> 16) & 0xff;
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/* byte offset format: [offsetSize][i2cAddr][offsetHigh][offsetLow] */
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i2c_addr = (*ppos >> 16) & 0xffff;
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offset = *ppos & 0xffff;
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total_read = i2c_read(ppd, target, i2c_addr, offset, buff, count);
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@ -71,14 +71,6 @@ static int __i2c_write(struct hfi1_pportdata *ppd, u32 target, int i2c_addr,
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int ret, cnt;
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u8 *buff = bp;
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/* Make sure TWSI bus is in sane state. */
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ret = hfi1_twsi_reset(dd, target);
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if (ret) {
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hfi1_dev_porterr(dd, ppd->port,
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"I2C interface Reset for write failed\n");
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return -EIO;
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}
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cnt = 0;
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while (cnt < len) {
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int wlen = len - cnt;
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@ -106,11 +98,22 @@ int i2c_write(struct hfi1_pportdata *ppd, u32 target, int i2c_addr, int offset,
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int ret;
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ret = mutex_lock_interruptible(&dd->qsfp_i2c_mutex);
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if (!ret) {
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ret = __i2c_write(ppd, target, i2c_addr, offset, bp, len);
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mutex_unlock(&dd->qsfp_i2c_mutex);
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if (ret)
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return ret;
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/* make sure the TWSI bus is in a sane state */
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ret = hfi1_twsi_reset(ppd->dd, target);
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if (ret) {
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hfi1_dev_porterr(ppd->dd, ppd->port,
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"I2C write interface reset failed\n");
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ret = -EIO;
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goto done;
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}
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ret = __i2c_write(ppd, target, i2c_addr, offset, bp, len);
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done:
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mutex_unlock(&dd->qsfp_i2c_mutex);
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return ret;
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}
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@ -125,16 +128,6 @@ static int __i2c_read(struct hfi1_pportdata *ppd, u32 target, int i2c_addr,
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int stuck = 0;
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u8 *buff = bp;
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/* Make sure TWSI bus is in sane state. */
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ret = hfi1_twsi_reset(dd, target);
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if (ret) {
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hfi1_dev_porterr(dd, ppd->port,
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"I2C interface Reset for read failed\n");
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ret = -EIO;
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stuck = 1;
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goto exit;
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}
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cnt = 0;
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while (cnt < len) {
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int rlen = len - cnt;
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@ -178,11 +171,22 @@ int i2c_read(struct hfi1_pportdata *ppd, u32 target, int i2c_addr, int offset,
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int ret;
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ret = mutex_lock_interruptible(&dd->qsfp_i2c_mutex);
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if (!ret) {
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ret = __i2c_read(ppd, target, i2c_addr, offset, bp, len);
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mutex_unlock(&dd->qsfp_i2c_mutex);
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if (ret)
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return ret;
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/* make sure the TWSI bus is in a sane state */
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ret = hfi1_twsi_reset(ppd->dd, target);
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if (ret) {
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hfi1_dev_porterr(ppd->dd, ppd->port,
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"I2C read interface reset failed\n");
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ret = -EIO;
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goto done;
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}
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ret = __i2c_read(ppd, target, i2c_addr, offset, bp, len);
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done:
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mutex_unlock(&dd->qsfp_i2c_mutex);
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return ret;
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}
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@ -203,6 +207,15 @@ int qsfp_write(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp,
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if (ret)
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return ret;
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/* make sure the TWSI bus is in a sane state */
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ret = hfi1_twsi_reset(ppd->dd, target);
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if (ret) {
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hfi1_dev_porterr(ppd->dd, ppd->port,
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"QSFP write interface reset failed\n");
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mutex_unlock(&ppd->dd->qsfp_i2c_mutex);
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return -EIO;
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}
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while (count < len) {
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/*
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* Set the qsfp page based on a zero-based addresss
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@ -210,8 +223,8 @@ int qsfp_write(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp,
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*/
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page = (u8)(addr / QSFP_PAGESIZE);
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ret = __i2c_write(ppd, target, QSFP_DEV,
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QSFP_PAGE_SELECT_BYTE_OFFS, &page, 1);
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ret = __i2c_write(ppd, target, QSFP_DEV | QSFP_OFFSET_SIZE,
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QSFP_PAGE_SELECT_BYTE_OFFS, &page, 1);
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if (ret != 1) {
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hfi1_dev_porterr(
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ppd->dd,
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@ -227,8 +240,8 @@ int qsfp_write(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp,
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if (((addr % QSFP_RW_BOUNDARY) + nwrite) > QSFP_RW_BOUNDARY)
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nwrite = QSFP_RW_BOUNDARY - (addr % QSFP_RW_BOUNDARY);
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ret = __i2c_write(ppd, target, QSFP_DEV, offset, bp + count,
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nwrite);
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ret = __i2c_write(ppd, target, QSFP_DEV | QSFP_OFFSET_SIZE,
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offset, bp + count, nwrite);
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if (ret <= 0) /* stop on error or nothing written */
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break;
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@ -260,14 +273,23 @@ int qsfp_read(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp,
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if (ret)
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return ret;
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/* make sure the TWSI bus is in a sane state */
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ret = hfi1_twsi_reset(ppd->dd, target);
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if (ret) {
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hfi1_dev_porterr(ppd->dd, ppd->port,
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"QSFP read interface reset failed\n");
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mutex_unlock(&ppd->dd->qsfp_i2c_mutex);
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return -EIO;
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}
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while (count < len) {
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/*
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* Set the qsfp page based on a zero-based address
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* and a page size of QSFP_PAGESIZE bytes.
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*/
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page = (u8)(addr / QSFP_PAGESIZE);
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ret = __i2c_write(ppd, target, QSFP_DEV,
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QSFP_PAGE_SELECT_BYTE_OFFS, &page, 1);
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ret = __i2c_write(ppd, target, QSFP_DEV | QSFP_OFFSET_SIZE,
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QSFP_PAGE_SELECT_BYTE_OFFS, &page, 1);
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if (ret != 1) {
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hfi1_dev_porterr(
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ppd->dd,
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@ -283,8 +305,10 @@ int qsfp_read(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp,
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if (((addr % QSFP_RW_BOUNDARY) + nread) > QSFP_RW_BOUNDARY)
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nread = QSFP_RW_BOUNDARY - (addr % QSFP_RW_BOUNDARY);
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ret = __i2c_read(ppd, target, QSFP_DEV, offset, bp + count,
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nread);
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/* QSFPs require a 5-10msec delay after write operations */
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mdelay(5);
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ret = __i2c_read(ppd, target, QSFP_DEV | QSFP_OFFSET_SIZE,
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offset, bp + count, nread);
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if (ret <= 0) /* stop on error or nothing read */
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break;
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@ -70,6 +70,10 @@
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/* Reads/writes cannot cross 128 byte boundaries */
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#define QSFP_RW_BOUNDARY 128
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/* number of bytes in i2c offset for QSFP devices */
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#define __QSFP_OFFSET_SIZE 1 /* num address bytes */
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#define QSFP_OFFSET_SIZE (__QSFP_OFFSET_SIZE << 8) /* shifted value */
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/* Defined fields that Intel requires of qualified cables */
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/* Byte 0 is Identifier, not checked */
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/* Byte 1 is reserved "status MSB" */
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@ -365,17 +365,25 @@ static int twsi_wr(struct hfi1_devdata *dd, u32 target, int data, int flags)
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* HFI1_TWSI_NO_DEV and does the correct operation for the legacy part,
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* which responded to all TWSI device codes, interpreting them as
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* address within device. On all other devices found on board handled by
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* this driver, the device is followed by a one-byte "address" which selects
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* this driver, the device is followed by a N-byte "address" which selects
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* the "register" or "offset" within the device from which data should
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* be read.
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*/
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int hfi1_twsi_blk_rd(struct hfi1_devdata *dd, u32 target, int dev, int addr,
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void *buffer, int len)
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{
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int ret;
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u8 *bp = buffer;
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int ret = 1;
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int i;
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int offset_size;
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ret = 1;
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/* obtain the offset size, strip it from the device address */
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offset_size = (dev >> 8) & 0xff;
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dev &= 0xff;
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/* allow at most a 2 byte offset */
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if (offset_size > 2)
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goto bail;
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if (dev == HFI1_TWSI_NO_DEV) {
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/* legacy not-really-I2C */
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@ -383,34 +391,29 @@ int hfi1_twsi_blk_rd(struct hfi1_devdata *dd, u32 target, int dev, int addr,
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ret = twsi_wr(dd, target, addr, HFI1_TWSI_START);
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} else {
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/* Actual I2C */
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ret = twsi_wr(dd, target, dev | WRITE_CMD, HFI1_TWSI_START);
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if (ret) {
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stop_cmd(dd, target);
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ret = 1;
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goto bail;
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}
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/*
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* SFF spec claims we do _not_ stop after the addr
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* but simply issue a start with the "read" dev-addr.
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* Since we are implicitly waiting for ACK here,
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* we need t_buf (nominally 20uSec) before that start,
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* and cannot rely on the delay built in to the STOP
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*/
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ret = twsi_wr(dd, target, addr, 0);
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udelay(TWSI_BUF_WAIT_USEC);
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if (offset_size) {
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ret = twsi_wr(dd, target,
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dev | WRITE_CMD, HFI1_TWSI_START);
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if (ret) {
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stop_cmd(dd, target);
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goto bail;
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}
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if (ret) {
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dd_dev_err(dd,
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"Failed to write interface read addr %02X\n",
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addr);
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ret = 1;
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goto bail;
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for (i = 0; i < offset_size; i++) {
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ret = twsi_wr(dd, target,
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(addr >> (i * 8)) & 0xff, 0);
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udelay(TWSI_BUF_WAIT_USEC);
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if (ret) {
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dd_dev_err(dd, "Failed to write byte %d of offset 0x%04X\n",
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i, addr);
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goto bail;
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}
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}
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}
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ret = twsi_wr(dd, target, dev | READ_CMD, HFI1_TWSI_START);
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}
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if (ret) {
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stop_cmd(dd, target);
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ret = 1;
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goto bail;
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}
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@ -442,76 +445,55 @@ bail:
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* HFI1_TWSI_NO_DEV and does the correct operation for the legacy part,
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* which responded to all TWSI device codes, interpreting them as
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* address within device. On all other devices found on board handled by
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* this driver, the device is followed by a one-byte "address" which selects
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* this driver, the device is followed by a N-byte "address" which selects
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* the "register" or "offset" within the device to which data should
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* be written.
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*/
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int hfi1_twsi_blk_wr(struct hfi1_devdata *dd, u32 target, int dev, int addr,
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const void *buffer, int len)
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{
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int sub_len;
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const u8 *bp = buffer;
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int max_wait_time, i;
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int ret = 1;
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int i;
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int offset_size;
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while (len > 0) {
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if (dev == HFI1_TWSI_NO_DEV) {
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if (twsi_wr(dd, target, (addr << 1) | WRITE_CMD,
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HFI1_TWSI_START)) {
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goto failed_write;
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}
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} else {
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/* Real I2C */
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if (twsi_wr(dd, target,
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dev | WRITE_CMD, HFI1_TWSI_START))
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goto failed_write;
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ret = twsi_wr(dd, target, addr, 0);
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if (ret) {
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dd_dev_err(dd,
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"Failed to write interface write addr %02X\n",
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addr);
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goto failed_write;
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}
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/* obtain the offset size, strip it from the device address */
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offset_size = (dev >> 8) & 0xff;
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dev &= 0xff;
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/* allow at most a 2 byte offset */
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if (offset_size > 2)
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goto bail;
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if (dev == HFI1_TWSI_NO_DEV) {
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if (twsi_wr(dd, target, (addr << 1) | WRITE_CMD,
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HFI1_TWSI_START)) {
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goto failed_write;
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}
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sub_len = min(len, 4);
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addr += sub_len;
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len -= sub_len;
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for (i = 0; i < sub_len; i++)
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if (twsi_wr(dd, target, *bp++, 0))
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goto failed_write;
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stop_cmd(dd, target);
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/*
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* Wait for write complete by waiting for a successful
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* read (the chip replies with a zero after the write
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* cmd completes, and before it writes to the eeprom.
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* The startcmd for the read will fail the ack until
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* the writes have completed. We do this inline to avoid
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* the debug prints that are in the real read routine
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* if the startcmd fails.
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* We also use the proper device address, so it doesn't matter
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* whether we have real eeprom_dev. Legacy likes any address.
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*/
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max_wait_time = 100;
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while (twsi_wr(dd, target,
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dev | READ_CMD, HFI1_TWSI_START)) {
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stop_cmd(dd, target);
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if (!--max_wait_time)
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goto failed_write;
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}
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/* now read (and ignore) the resulting byte */
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rd_byte(dd, target, 1);
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} else {
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/* Real I2C */
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if (twsi_wr(dd, target, dev | WRITE_CMD, HFI1_TWSI_START))
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goto failed_write;
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}
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for (i = 0; i < offset_size; i++) {
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ret = twsi_wr(dd, target, (addr >> (i * 8)) & 0xff, 0);
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udelay(TWSI_BUF_WAIT_USEC);
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if (ret) {
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dd_dev_err(dd, "Failed to write byte %d of offset 0x%04X\n",
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i, addr);
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goto bail;
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}
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}
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for (i = 0; i < len; i++)
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if (twsi_wr(dd, target, *bp++, 0))
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goto failed_write;
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ret = 0;
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goto bail;
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failed_write:
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stop_cmd(dd, target);
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ret = 1;
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bail:
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return ret;
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