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s390/zcrypt: Integrate ap_asm.h into include/asm/ap.h.
Move all the inline functions from the ap bus header file ap_asm.h into the in-kernel api header file arch/s390/include/asm/ap.h so that KVM can make use of all the low level AP functions. Signed-off-by: Harald Freudenberger <freude@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
This commit is contained in:
Harald Freudenberger
Martin Schwidefsky
parent
4a07750ba8
commit
f1b0a4343c
@ -46,6 +46,50 @@ struct ap_queue_status {
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unsigned int _pad2 : 16;
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};
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/**
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* ap_intructions_available() - Test if AP instructions are available.
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*
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* Returns 0 if the AP instructions are installed.
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*/
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static inline int ap_instructions_available(void)
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{
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register unsigned long reg0 asm ("0") = AP_MKQID(0, 0);
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register unsigned long reg1 asm ("1") = -ENODEV;
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register unsigned long reg2 asm ("2");
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asm volatile(
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" .long 0xb2af0000\n" /* PQAP(TAPQ) */
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"0: la %0,0\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: "+d" (reg1), "=d" (reg2)
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: "d" (reg0)
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: "cc");
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return reg1;
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}
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/**
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* ap_tapq(): Test adjunct processor queue.
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* @qid: The AP queue number
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* @info: Pointer to queue descriptor
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*
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* Returns AP queue status structure.
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*/
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static inline struct ap_queue_status ap_tapq(ap_qid_t qid, unsigned long *info)
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{
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register unsigned long reg0 asm ("0") = qid;
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register struct ap_queue_status reg1 asm ("1");
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register unsigned long reg2 asm ("2");
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asm volatile(".long 0xb2af0000" /* PQAP(TAPQ) */
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: "=d" (reg1), "=d" (reg2)
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: "d" (reg0)
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: "cc");
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if (info)
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*info = reg2;
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return reg1;
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}
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/**
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* ap_test_queue(): Test adjunct processor queue.
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* @qid: The AP queue number
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@ -54,10 +98,57 @@ struct ap_queue_status {
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*
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* Returns AP queue status structure.
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*/
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struct ap_queue_status ap_test_queue(ap_qid_t qid,
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int tbit,
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unsigned long *info);
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static inline struct ap_queue_status ap_test_queue(ap_qid_t qid,
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int tbit,
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unsigned long *info)
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{
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if (tbit)
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qid |= 1UL << 23; /* set T bit*/
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return ap_tapq(qid, info);
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}
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/**
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* ap_pqap_rapq(): Reset adjunct processor queue.
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* @qid: The AP queue number
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*
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* Returns AP queue status structure.
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*/
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static inline struct ap_queue_status ap_rapq(ap_qid_t qid)
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{
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register unsigned long reg0 asm ("0") = qid | (1UL << 24);
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register struct ap_queue_status reg1 asm ("1");
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asm volatile(
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".long 0xb2af0000" /* PQAP(RAPQ) */
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: "=d" (reg1)
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: "d" (reg0)
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: "cc");
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return reg1;
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}
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/**
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* ap_pqap_zapq(): Reset and zeroize adjunct processor queue.
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* @qid: The AP queue number
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*
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* Returns AP queue status structure.
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*/
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static inline struct ap_queue_status ap_zapq(ap_qid_t qid)
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{
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register unsigned long reg0 asm ("0") = qid | (2UL << 24);
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register struct ap_queue_status reg1 asm ("1");
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asm volatile(
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".long 0xb2af0000" /* PQAP(ZAPQ) */
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: "=d" (reg1)
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: "d" (reg0)
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: "cc");
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return reg1;
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}
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/**
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* struct ap_config_info - convenience struct for AP crypto
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* config info as returned by the ap_qci() function.
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*/
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struct ap_config_info {
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unsigned int apsc : 1; /* S bit */
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unsigned int apxa : 1; /* N bit */
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@ -74,50 +165,189 @@ struct ap_config_info {
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unsigned char _reserved4[16];
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} __aligned(8);
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/*
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* ap_query_configuration(): Fetch cryptographic config info
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/**
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* ap_qci(): Get AP configuration data
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*
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* Returns the ap configuration info fetched via PQAP(QCI).
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* On success 0 is returned, on failure a negative errno
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* is returned, e.g. if the PQAP(QCI) instruction is not
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* available, the return value will be -EOPNOTSUPP.
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* Returns 0 on success, or -EOPNOTSUPP.
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*/
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int ap_query_configuration(struct ap_config_info *info);
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static inline int ap_qci(struct ap_config_info *config)
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{
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register unsigned long reg0 asm ("0") = 4UL << 24;
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register unsigned long reg1 asm ("1") = -EOPNOTSUPP;
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register struct ap_config_info *reg2 asm ("2") = config;
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asm volatile(
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".long 0xb2af0000\n" /* PQAP(QCI) */
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"0: la %0,0\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: "+d" (reg1)
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: "d" (reg0), "d" (reg2)
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: "cc", "memory");
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return reg1;
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}
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/*
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* struct ap_qirq_ctrl - convenient struct for easy invocation
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* of the ap_queue_irq_ctrl() function. This struct is passed
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* as GR1 parameter to the PQAP(AQIC) instruction. For details
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* please see the AR documentation.
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* of the ap_aqic() function. This struct is passed as GR1
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* parameter to the PQAP(AQIC) instruction. For details please
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* see the AR documentation.
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*/
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struct ap_qirq_ctrl {
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unsigned int _res1 : 8;
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unsigned int zone : 8; /* zone info */
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unsigned int ir : 1; /* ir flag: enable (1) or disable (0) irq */
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unsigned int zone : 8; /* zone info */
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unsigned int ir : 1; /* ir flag: enable (1) or disable (0) irq */
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unsigned int _res2 : 4;
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unsigned int gisc : 3; /* guest isc field */
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unsigned int gisc : 3; /* guest isc field */
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unsigned int _res3 : 6;
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unsigned int gf : 2; /* gisa format */
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unsigned int gf : 2; /* gisa format */
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unsigned int _res4 : 1;
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unsigned int gisa : 27; /* gisa origin */
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unsigned int gisa : 27; /* gisa origin */
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unsigned int _res5 : 1;
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unsigned int isc : 3; /* irq sub class */
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unsigned int isc : 3; /* irq sub class */
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};
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/**
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* ap_queue_irq_ctrl(): Control interruption on a AP queue.
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* ap_aqic(): Control interruption for a specific AP.
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* @qid: The AP queue number
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* @qirqctrl: struct ap_qirq_ctrl, see above
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* @qirqctrl: struct ap_qirq_ctrl (64 bit value)
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* @ind: The notification indicator byte
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*
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* Returns AP queue status.
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*
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* Control interruption on the given AP queue.
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* Just a simple wrapper function for the low level PQAP(AQIC)
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* instruction available for other kernel modules.
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*/
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struct ap_queue_status ap_queue_irq_ctrl(ap_qid_t qid,
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struct ap_qirq_ctrl qirqctrl,
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void *ind);
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static inline struct ap_queue_status ap_aqic(ap_qid_t qid,
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struct ap_qirq_ctrl qirqctrl,
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void *ind)
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{
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register unsigned long reg0 asm ("0") = qid | (3UL << 24);
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register struct ap_qirq_ctrl reg1_in asm ("1") = qirqctrl;
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register struct ap_queue_status reg1_out asm ("1");
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register void *reg2 asm ("2") = ind;
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asm volatile(
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".long 0xb2af0000" /* PQAP(AQIC) */
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: "=d" (reg1_out)
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: "d" (reg0), "d" (reg1_in), "d" (reg2)
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: "cc");
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return reg1_out;
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}
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/*
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* union ap_qact_ap_info - used together with the
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* ap_aqic() function to provide a convenient way
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* to handle the ap info needed by the qact function.
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*/
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union ap_qact_ap_info {
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unsigned long val;
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struct {
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unsigned int : 3;
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unsigned int mode : 3;
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unsigned int : 26;
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unsigned int cat : 8;
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unsigned int : 8;
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unsigned char ver[2];
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};
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};
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/**
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* ap_qact(): Query AP combatibility type.
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* @qid: The AP queue number
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* @apinfo: On input the info about the AP queue. On output the
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* alternate AP queue info provided by the qact function
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* in GR2 is stored in.
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*
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* Returns AP queue status. Check response_code field for failures.
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*/
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static inline struct ap_queue_status ap_qact(ap_qid_t qid, int ifbit,
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union ap_qact_ap_info *apinfo)
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{
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register unsigned long reg0 asm ("0") = qid | (5UL << 24)
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| ((ifbit & 0x01) << 22);
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register unsigned long reg1_in asm ("1") = apinfo->val;
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register struct ap_queue_status reg1_out asm ("1");
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register unsigned long reg2 asm ("2");
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asm volatile(
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".long 0xb2af0000" /* PQAP(QACT) */
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: "+d" (reg1_in), "=d" (reg1_out), "=d" (reg2)
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: "d" (reg0)
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: "cc");
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apinfo->val = reg2;
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return reg1_out;
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}
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/**
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* ap_nqap(): Send message to adjunct processor queue.
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* @qid: The AP queue number
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* @psmid: The program supplied message identifier
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* @msg: The message text
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* @length: The message length
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*
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* Returns AP queue status structure.
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* Condition code 1 on NQAP can't happen because the L bit is 1.
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* Condition code 2 on NQAP also means the send is incomplete,
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* because a segment boundary was reached. The NQAP is repeated.
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*/
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static inline struct ap_queue_status ap_nqap(ap_qid_t qid,
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unsigned long long psmid,
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void *msg, size_t length)
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{
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register unsigned long reg0 asm ("0") = qid | 0x40000000UL;
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register struct ap_queue_status reg1 asm ("1");
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register unsigned long reg2 asm ("2") = (unsigned long) msg;
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register unsigned long reg3 asm ("3") = (unsigned long) length;
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register unsigned long reg4 asm ("4") = (unsigned int) (psmid >> 32);
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register unsigned long reg5 asm ("5") = psmid & 0xffffffff;
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asm volatile (
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"0: .long 0xb2ad0042\n" /* NQAP */
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" brc 2,0b"
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: "+d" (reg0), "=d" (reg1), "+d" (reg2), "+d" (reg3)
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: "d" (reg4), "d" (reg5)
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: "cc", "memory");
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return reg1;
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}
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/**
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* ap_dqap(): Receive message from adjunct processor queue.
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* @qid: The AP queue number
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* @psmid: Pointer to program supplied message identifier
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* @msg: The message text
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* @length: The message length
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*
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* Returns AP queue status structure.
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* Condition code 1 on DQAP means the receive has taken place
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* but only partially. The response is incomplete, hence the
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* DQAP is repeated.
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* Condition code 2 on DQAP also means the receive is incomplete,
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* this time because a segment boundary was reached. Again, the
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* DQAP is repeated.
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* Note that gpr2 is used by the DQAP instruction to keep track of
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* any 'residual' length, in case the instruction gets interrupted.
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* Hence it gets zeroed before the instruction.
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*/
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static inline struct ap_queue_status ap_dqap(ap_qid_t qid,
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unsigned long long *psmid,
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void *msg, size_t length)
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{
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register unsigned long reg0 asm("0") = qid | 0x80000000UL;
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register struct ap_queue_status reg1 asm ("1");
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register unsigned long reg2 asm("2") = 0UL;
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register unsigned long reg4 asm("4") = (unsigned long) msg;
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register unsigned long reg5 asm("5") = (unsigned long) length;
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register unsigned long reg6 asm("6") = 0UL;
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register unsigned long reg7 asm("7") = 0UL;
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asm volatile(
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"0: .long 0xb2ae0064\n" /* DQAP */
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" brc 6,0b\n"
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: "+d" (reg0), "=d" (reg1), "+d" (reg2),
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"+d" (reg4), "+d" (reg5), "+d" (reg6), "+d" (reg7)
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: : "cc", "memory");
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*psmid = (((unsigned long long) reg6) << 32) + reg7;
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return reg1;
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}
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#endif /* _ASM_S390_AP_H_ */
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@ -1,261 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright IBM Corp. 2016
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* Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
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*
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* Adjunct processor bus inline assemblies.
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*/
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#ifndef _AP_ASM_H_
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#define _AP_ASM_H_
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#include <asm/isc.h>
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/**
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* ap_intructions_available() - Test if AP instructions are available.
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*
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* Returns 0 if the AP instructions are installed.
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*/
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static inline int ap_instructions_available(void)
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{
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register unsigned long reg0 asm ("0") = AP_MKQID(0, 0);
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register unsigned long reg1 asm ("1") = -ENODEV;
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register unsigned long reg2 asm ("2");
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asm volatile(
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" .long 0xb2af0000\n" /* PQAP(TAPQ) */
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"0: la %0,0\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: "+d" (reg1), "=d" (reg2)
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: "d" (reg0)
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: "cc");
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return reg1;
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}
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/**
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* ap_tapq(): Test adjunct processor queue.
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* @qid: The AP queue number
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* @info: Pointer to queue descriptor
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*
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* Returns AP queue status structure.
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*/
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static inline struct ap_queue_status ap_tapq(ap_qid_t qid, unsigned long *info)
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{
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register unsigned long reg0 asm ("0") = qid;
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register struct ap_queue_status reg1 asm ("1");
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register unsigned long reg2 asm ("2");
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asm volatile(".long 0xb2af0000" /* PQAP(TAPQ) */
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: "=d" (reg1), "=d" (reg2)
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: "d" (reg0)
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: "cc");
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if (info)
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*info = reg2;
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return reg1;
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}
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/**
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* ap_pqap_rapq(): Reset adjunct processor queue.
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* @qid: The AP queue number
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*
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* Returns AP queue status structure.
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*/
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static inline struct ap_queue_status ap_rapq(ap_qid_t qid)
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{
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register unsigned long reg0 asm ("0") = qid | (1UL << 24);
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register struct ap_queue_status reg1 asm ("1");
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asm volatile(
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".long 0xb2af0000" /* PQAP(RAPQ) */
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: "=d" (reg1)
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: "d" (reg0)
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: "cc");
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return reg1;
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}
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/**
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* ap_pqap_zapq(): Reset and zeroize adjunct processor queue.
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* @qid: The AP queue number
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*
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* Returns AP queue status structure.
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*/
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static inline struct ap_queue_status ap_zapq(ap_qid_t qid)
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{
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register unsigned long reg0 asm ("0") = qid | (2UL << 24);
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register struct ap_queue_status reg1 asm ("1");
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asm volatile(
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".long 0xb2af0000" /* PQAP(ZAPQ) */
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: "=d" (reg1)
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: "d" (reg0)
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: "cc");
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return reg1;
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}
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/**
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* ap_aqic(): Control interruption for a specific AP.
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* @qid: The AP queue number
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* @qirqctrl: struct ap_qirq_ctrl (64 bit value)
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* @ind: The notification indicator byte
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*
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* Returns AP queue status.
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*/
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static inline struct ap_queue_status ap_aqic(ap_qid_t qid,
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struct ap_qirq_ctrl qirqctrl,
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void *ind)
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{
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register unsigned long reg0 asm ("0") = qid | (3UL << 24);
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register struct ap_qirq_ctrl reg1_in asm ("1") = qirqctrl;
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register struct ap_queue_status reg1_out asm ("1");
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register void *reg2 asm ("2") = ind;
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asm volatile(
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".long 0xb2af0000" /* PQAP(AQIC) */
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: "=d" (reg1_out)
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: "d" (reg0), "d" (reg1_in), "d" (reg2)
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: "cc");
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return reg1_out;
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}
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/**
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* ap_qci(): Get AP configuration data
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*
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* Returns 0 on success, or -EOPNOTSUPP.
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*/
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static inline int ap_qci(void *config)
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{
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register unsigned long reg0 asm ("0") = 4UL << 24;
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register unsigned long reg1 asm ("1") = -EINVAL;
|
||||
register void *reg2 asm ("2") = (void *) config;
|
||||
|
||||
asm volatile(
|
||||
".long 0xb2af0000\n" /* PQAP(QCI) */
|
||||
"0: la %0,0\n"
|
||||
"1:\n"
|
||||
EX_TABLE(0b, 1b)
|
||||
: "+d" (reg1)
|
||||
: "d" (reg0), "d" (reg2)
|
||||
: "cc", "memory");
|
||||
|
||||
return reg1;
|
||||
}
|
||||
|
||||
/*
|
||||
* union ap_qact_ap_info - used together with the
|
||||
* ap_aqic() function to provide a convenient way
|
||||
* to handle the ap info needed by the qact function.
|
||||
*/
|
||||
union ap_qact_ap_info {
|
||||
unsigned long val;
|
||||
struct {
|
||||
unsigned int : 3;
|
||||
unsigned int mode : 3;
|
||||
unsigned int : 26;
|
||||
unsigned int cat : 8;
|
||||
unsigned int : 8;
|
||||
unsigned char ver[2];
|
||||
};
|
||||
};
|
||||
|
||||
/**
|
||||
* ap_qact(): Query AP combatibility type.
|
||||
* @qid: The AP queue number
|
||||
* @apinfo: On input the info about the AP queue. On output the
|
||||
* alternate AP queue info provided by the qact function
|
||||
* in GR2 is stored in.
|
||||
*
|
||||
* Returns AP queue status. Check response_code field for failures.
|
||||
*/
|
||||
static inline struct ap_queue_status ap_qact(ap_qid_t qid, int ifbit,
|
||||
union ap_qact_ap_info *apinfo)
|
||||
{
|
||||
register unsigned long reg0 asm ("0") = qid | (5UL << 24)
|
||||
| ((ifbit & 0x01) << 22);
|
||||
register unsigned long reg1_in asm ("1") = apinfo->val;
|
||||
register struct ap_queue_status reg1_out asm ("1");
|
||||
register unsigned long reg2 asm ("2");
|
||||
|
||||
asm volatile(
|
||||
".long 0xb2af0000" /* PQAP(QACT) */
|
||||
: "+d" (reg1_in), "=d" (reg1_out), "=d" (reg2)
|
||||
: "d" (reg0)
|
||||
: "cc");
|
||||
apinfo->val = reg2;
|
||||
return reg1_out;
|
||||
}
|
||||
|
||||
/**
|
||||
* ap_nqap(): Send message to adjunct processor queue.
|
||||
* @qid: The AP queue number
|
||||
* @psmid: The program supplied message identifier
|
||||
* @msg: The message text
|
||||
* @length: The message length
|
||||
*
|
||||
* Returns AP queue status structure.
|
||||
* Condition code 1 on NQAP can't happen because the L bit is 1.
|
||||
* Condition code 2 on NQAP also means the send is incomplete,
|
||||
* because a segment boundary was reached. The NQAP is repeated.
|
||||
*/
|
||||
static inline struct ap_queue_status ap_nqap(ap_qid_t qid,
|
||||
unsigned long long psmid,
|
||||
void *msg, size_t length)
|
||||
{
|
||||
register unsigned long reg0 asm ("0") = qid | 0x40000000UL;
|
||||
register struct ap_queue_status reg1 asm ("1");
|
||||
register unsigned long reg2 asm ("2") = (unsigned long) msg;
|
||||
register unsigned long reg3 asm ("3") = (unsigned long) length;
|
||||
register unsigned long reg4 asm ("4") = (unsigned int) (psmid >> 32);
|
||||
register unsigned long reg5 asm ("5") = psmid & 0xffffffff;
|
||||
|
||||
asm volatile (
|
||||
"0: .long 0xb2ad0042\n" /* NQAP */
|
||||
" brc 2,0b"
|
||||
: "+d" (reg0), "=d" (reg1), "+d" (reg2), "+d" (reg3)
|
||||
: "d" (reg4), "d" (reg5)
|
||||
: "cc", "memory");
|
||||
return reg1;
|
||||
}
|
||||
|
||||
/**
|
||||
* ap_dqap(): Receive message from adjunct processor queue.
|
||||
* @qid: The AP queue number
|
||||
* @psmid: Pointer to program supplied message identifier
|
||||
* @msg: The message text
|
||||
* @length: The message length
|
||||
*
|
||||
* Returns AP queue status structure.
|
||||
* Condition code 1 on DQAP means the receive has taken place
|
||||
* but only partially. The response is incomplete, hence the
|
||||
* DQAP is repeated.
|
||||
* Condition code 2 on DQAP also means the receive is incomplete,
|
||||
* this time because a segment boundary was reached. Again, the
|
||||
* DQAP is repeated.
|
||||
* Note that gpr2 is used by the DQAP instruction to keep track of
|
||||
* any 'residual' length, in case the instruction gets interrupted.
|
||||
* Hence it gets zeroed before the instruction.
|
||||
*/
|
||||
static inline struct ap_queue_status ap_dqap(ap_qid_t qid,
|
||||
unsigned long long *psmid,
|
||||
void *msg, size_t length)
|
||||
{
|
||||
register unsigned long reg0 asm("0") = qid | 0x80000000UL;
|
||||
register struct ap_queue_status reg1 asm ("1");
|
||||
register unsigned long reg2 asm("2") = 0UL;
|
||||
register unsigned long reg4 asm("4") = (unsigned long) msg;
|
||||
register unsigned long reg5 asm("5") = (unsigned long) length;
|
||||
register unsigned long reg6 asm("6") = 0UL;
|
||||
register unsigned long reg7 asm("7") = 0UL;
|
||||
|
||||
|
||||
asm volatile(
|
||||
"0: .long 0xb2ae0064\n" /* DQAP */
|
||||
" brc 6,0b\n"
|
||||
: "+d" (reg0), "=d" (reg1), "+d" (reg2),
|
||||
"+d" (reg4), "+d" (reg5), "+d" (reg6), "+d" (reg7)
|
||||
: : "cc", "memory");
|
||||
*psmid = (((unsigned long long) reg6) << 32) + reg7;
|
||||
return reg1;
|
||||
}
|
||||
|
||||
#endif /* _AP_ASM_H_ */
|
||||
@ -36,7 +36,6 @@
|
||||
#include <linux/debugfs.h>
|
||||
|
||||
#include "ap_bus.h"
|
||||
#include "ap_asm.h"
|
||||
#include "ap_debug.h"
|
||||
|
||||
/*
|
||||
@ -174,24 +173,6 @@ static inline int ap_qact_available(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* ap_test_queue(): Test adjunct processor queue.
|
||||
* @qid: The AP queue number
|
||||
* @tbit: Test facilities bit
|
||||
* @info: Pointer to queue descriptor
|
||||
*
|
||||
* Returns AP queue status structure.
|
||||
*/
|
||||
struct ap_queue_status ap_test_queue(ap_qid_t qid,
|
||||
int tbit,
|
||||
unsigned long *info)
|
||||
{
|
||||
if (tbit)
|
||||
qid |= 1UL << 23; /* set T bit*/
|
||||
return ap_tapq(qid, info);
|
||||
}
|
||||
EXPORT_SYMBOL(ap_test_queue);
|
||||
|
||||
/*
|
||||
* ap_query_configuration(): Fetch cryptographic config info
|
||||
*
|
||||
@ -200,7 +181,7 @@ EXPORT_SYMBOL(ap_test_queue);
|
||||
* is returned, e.g. if the PQAP(QCI) instruction is not
|
||||
* available, the return value will be -EOPNOTSUPP.
|
||||
*/
|
||||
int ap_query_configuration(struct ap_config_info *info)
|
||||
static inline int ap_query_configuration(struct ap_config_info *info)
|
||||
{
|
||||
if (!ap_configuration_available())
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
@ -15,6 +15,7 @@
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/isc.h>
|
||||
#include <asm/ap.h>
|
||||
|
||||
#define AP_DEVICES 256 /* Number of AP devices. */
|
||||
|
||||
@ -14,7 +14,6 @@
|
||||
#include <asm/facility.h>
|
||||
|
||||
#include "ap_bus.h"
|
||||
#include "ap_asm.h"
|
||||
|
||||
/*
|
||||
* AP card related attributes.
|
||||
|
||||
@ -14,26 +14,6 @@
|
||||
#include <asm/facility.h>
|
||||
|
||||
#include "ap_bus.h"
|
||||
#include "ap_asm.h"
|
||||
|
||||
/**
|
||||
* ap_queue_irq_ctrl(): Control interruption on a AP queue.
|
||||
* @qirqctrl: struct ap_qirq_ctrl (64 bit value)
|
||||
* @ind: The notification indicator byte
|
||||
*
|
||||
* Returns AP queue status.
|
||||
*
|
||||
* Control interruption on the given AP queue.
|
||||
* Just a simple wrapper function for the low level PQAP(AQIC)
|
||||
* instruction available for other kernel modules.
|
||||
*/
|
||||
struct ap_queue_status ap_queue_irq_ctrl(ap_qid_t qid,
|
||||
struct ap_qirq_ctrl qirqctrl,
|
||||
void *ind)
|
||||
{
|
||||
return ap_aqic(qid, qirqctrl, ind);
|
||||
}
|
||||
EXPORT_SYMBOL(ap_queue_irq_ctrl);
|
||||
|
||||
/**
|
||||
* ap_queue_enable_interruption(): Enable interruption on an AP queue.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user