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cxgb4/cxgb4vf/csiostor: Cleanup SGE and PCI related register defines

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This patch cleansup remaining SGE related macros/register defines and all PCI
related ones that are defined in t4_regs.h and the affected files.

Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Hariprasad Shenai 2015-01-05 16:30:44 +05:30 committed by David S. Miller
parent f612b815d7
commit f061de42e6
13 changed files with 750 additions and 516 deletions
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68
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
View File

@ -1590,9 +1590,9 @@ static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
data += sizeof(struct queue_port_stats) / sizeof(u64);
if (!is_t4(adapter->params.chip)) {
t4_write_reg(adapter, SGE_STAT_CFG, STATSOURCE_T5(7));
val1 = t4_read_reg(adapter, SGE_STAT_TOTAL);
val2 = t4_read_reg(adapter, SGE_STAT_MATCH);
t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7));
val1 = t4_read_reg(adapter, SGE_STAT_TOTAL_A);
val2 = t4_read_reg(adapter, SGE_STAT_MATCH_A);
*data = val1 - val2;
data++;
*data = val2;
@ -3601,14 +3601,14 @@ unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
struct adapter *adap = netdev2adap(dev);
u32 v1, v2, lp_count, hp_count;
v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
if (is_t4(adap->params.chip)) {
lp_count = G_LP_COUNT(v1);
hp_count = G_HP_COUNT(v1);
lp_count = LP_COUNT_G(v1);
hp_count = HP_COUNT_G(v1);
} else {
lp_count = G_LP_COUNT_T5(v1);
hp_count = G_HP_COUNT_T5(v2);
lp_count = LP_COUNT_T5_G(v1);
hp_count = HP_COUNT_T5_G(v2);
}
return lpfifo ? lp_count : hp_count;
}
@ -3667,14 +3667,14 @@ int cxgb4_flush_eq_cache(struct net_device *dev)
int ret;
ret = t4_fwaddrspace_write(adap, adap->mbox,
0xe1000000 + A_SGE_CTXT_CMD, 0x20000000);
0xe1000000 + SGE_CTXT_CMD_A, 0x20000000);
return ret;
}
EXPORT_SYMBOL(cxgb4_flush_eq_cache);
static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
{
u32 addr = t4_read_reg(adap, A_SGE_DBQ_CTXT_BADDR) + 24 * qid + 8;
u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
__be64 indices;
int ret;
@ -3728,7 +3728,7 @@ void cxgb4_disable_db_coalescing(struct net_device *dev)
struct adapter *adap;
adap = netdev2adap(dev);
t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, NOCOALESCE_F,
t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, NOCOALESCE_F,
NOCOALESCE_F);
}
EXPORT_SYMBOL(cxgb4_disable_db_coalescing);
@ -3738,7 +3738,7 @@ void cxgb4_enable_db_coalescing(struct net_device *dev)
struct adapter *adap;
adap = netdev2adap(dev);
t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, NOCOALESCE_F, 0);
t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, NOCOALESCE_F, 0);
}
EXPORT_SYMBOL(cxgb4_enable_db_coalescing);
@ -3877,14 +3877,14 @@ static void drain_db_fifo(struct adapter *adap, int usecs)
u32 v1, v2, lp_count, hp_count;
do {
v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
if (is_t4(adap->params.chip)) {
lp_count = G_LP_COUNT(v1);
hp_count = G_HP_COUNT(v1);
lp_count = LP_COUNT_G(v1);
hp_count = HP_COUNT_G(v1);
} else {
lp_count = G_LP_COUNT_T5(v1);
hp_count = G_HP_COUNT_T5(v2);
lp_count = LP_COUNT_T5_G(v1);
hp_count = HP_COUNT_T5_G(v2);
}
if (lp_count == 0 && hp_count == 0)
@ -4044,7 +4044,7 @@ static void process_db_drop(struct work_struct *work)
t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
}
t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_DROPPED_DB, 0);
t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
}
void t4_db_full(struct adapter *adap)
@ -4871,16 +4871,16 @@ static void setup_memwin(struct adapter *adap)
mem_win2_base = MEMWIN2_BASE_T5;
mem_win2_aperture = MEMWIN2_APERTURE_T5;
}
t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0),
mem_win0_base | BIR(0) |
WINDOW(ilog2(MEMWIN0_APERTURE) - 10));
t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1),
mem_win1_base | BIR(0) |
WINDOW(ilog2(MEMWIN1_APERTURE) - 10));
t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2),
mem_win2_base | BIR(0) |
WINDOW(ilog2(mem_win2_aperture) - 10));
t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2));
t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 0),
mem_win0_base | BIR_V(0) |
WINDOW_V(ilog2(MEMWIN0_APERTURE) - 10));
t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 1),
mem_win1_base | BIR_V(0) |
WINDOW_V(ilog2(MEMWIN1_APERTURE) - 10));
t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 2),
mem_win2_base | BIR_V(0) |
WINDOW_V(ilog2(mem_win2_aperture) - 10));
t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 2));
}
static void setup_memwin_rdma(struct adapter *adap)
@ -4894,13 +4894,13 @@ static void setup_memwin_rdma(struct adapter *adap)
start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
t4_write_reg(adap,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 3),
start | BIR(1) | WINDOW(ilog2(sz_kb)));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
t4_write_reg(adap,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3),
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
adap->vres.ocq.start);
t4_read_reg(adap,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
}
}

78
drivers/net/ethernet/chelsio/cxgb4/sge.c
View File

@ -2098,7 +2098,7 @@ static irqreturn_t t4_intr_intx(int irq, void *cookie)
{
struct adapter *adap = cookie;
t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI), 0);
t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI_A), 0);
if (t4_slow_intr_handler(adap) | process_intrq(adap))
return IRQ_HANDLED;
return IRQ_NONE; /* probably shared interrupt */
@ -2145,9 +2145,9 @@ static void sge_rx_timer_cb(unsigned long data)
}
}
t4_write_reg(adap, SGE_DEBUG_INDEX, 13);
idma_same_state_cnt[0] = t4_read_reg(adap, SGE_DEBUG_DATA_HIGH);
idma_same_state_cnt[1] = t4_read_reg(adap, SGE_DEBUG_DATA_LOW);
t4_write_reg(adap, SGE_DEBUG_INDEX_A, 13);
idma_same_state_cnt[0] = t4_read_reg(adap, SGE_DEBUG_DATA_HIGH_A);
idma_same_state_cnt[1] = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A);
for (i = 0; i < 2; i++) {
u32 debug0, debug11;
@ -2191,12 +2191,12 @@ static void sge_rx_timer_cb(unsigned long data)
/* Read and save the SGE IDMA State and Queue ID information.
* We do this every time in case it changes across time ...
*/
t4_write_reg(adap, SGE_DEBUG_INDEX, 0);
debug0 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW);
t4_write_reg(adap, SGE_DEBUG_INDEX_A, 0);
debug0 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A);
s->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
t4_write_reg(adap, SGE_DEBUG_INDEX, 11);
debug11 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW);
t4_write_reg(adap, SGE_DEBUG_INDEX_A, 11);
debug11 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A);
s->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
CH_WARN(adap, "SGE idma%u, queue%u, maybe stuck state%u %dsecs (debug0=%#x, debug11=%#x)\n",
@ -2826,21 +2826,21 @@ static int t4_sge_init_soft(struct adapter *adap)
* Retrieve our RX interrupt holdoff timer values and counter
* threshold values from the SGE parameters.
*/
timer_value_0_and_1 = t4_read_reg(adap, SGE_TIMER_VALUE_0_AND_1);
timer_value_2_and_3 = t4_read_reg(adap, SGE_TIMER_VALUE_2_AND_3);
timer_value_4_and_5 = t4_read_reg(adap, SGE_TIMER_VALUE_4_AND_5);
timer_value_0_and_1 = t4_read_reg(adap, SGE_TIMER_VALUE_0_AND_1_A);
timer_value_2_and_3 = t4_read_reg(adap, SGE_TIMER_VALUE_2_AND_3_A);
timer_value_4_and_5 = t4_read_reg(adap, SGE_TIMER_VALUE_4_AND_5_A);
s->timer_val[0] = core_ticks_to_us(adap,
TIMERVALUE0_GET(timer_value_0_and_1));
TIMERVALUE0_G(timer_value_0_and_1));
s->timer_val[1] = core_ticks_to_us(adap,
TIMERVALUE1_GET(timer_value_0_and_1));
TIMERVALUE1_G(timer_value_0_and_1));
s->timer_val[2] = core_ticks_to_us(adap,
TIMERVALUE2_GET(timer_value_2_and_3));
TIMERVALUE2_G(timer_value_2_and_3));
s->timer_val[3] = core_ticks_to_us(adap,
TIMERVALUE3_GET(timer_value_2_and_3));
TIMERVALUE3_G(timer_value_2_and_3));
s->timer_val[4] = core_ticks_to_us(adap,
TIMERVALUE4_GET(timer_value_4_and_5));
TIMERVALUE4_G(timer_value_4_and_5));
s->timer_val[5] = core_ticks_to_us(adap,
TIMERVALUE5_GET(timer_value_4_and_5));
TIMERVALUE5_G(timer_value_4_and_5));
ingress_rx_threshold = t4_read_reg(adap, SGE_INGRESS_RX_THRESHOLD_A);
s->counter_val[0] = THRESHOLD_0_G(ingress_rx_threshold);
@ -2866,21 +2866,21 @@ static int t4_sge_init_hard(struct adapter *adap)
* and generate an interrupt when this occurs so we can recover.
*/
if (is_t4(adap->params.chip)) {
t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS,
V_HP_INT_THRESH(M_HP_INT_THRESH) |
V_LP_INT_THRESH(M_LP_INT_THRESH),
V_HP_INT_THRESH(dbfifo_int_thresh) |
V_LP_INT_THRESH(dbfifo_int_thresh));
t4_set_reg_field(adap, SGE_DBFIFO_STATUS_A,
HP_INT_THRESH_V(HP_INT_THRESH_M) |
LP_INT_THRESH_V(LP_INT_THRESH_M),
HP_INT_THRESH_V(dbfifo_int_thresh) |
LP_INT_THRESH_V(dbfifo_int_thresh));
} else {
t4_set_reg_field(adap, A_SGE_DBFIFO_STATUS,
V_LP_INT_THRESH_T5(M_LP_INT_THRESH_T5),
V_LP_INT_THRESH_T5(dbfifo_int_thresh));
t4_set_reg_field(adap, SGE_DBFIFO_STATUS2,
V_HP_INT_THRESH_T5(M_HP_INT_THRESH_T5),
V_HP_INT_THRESH_T5(dbfifo_int_thresh));
t4_set_reg_field(adap, SGE_DBFIFO_STATUS_A,
LP_INT_THRESH_T5_V(LP_INT_THRESH_T5_M),
LP_INT_THRESH_T5_V(dbfifo_int_thresh));
t4_set_reg_field(adap, SGE_DBFIFO_STATUS2_A,
HP_INT_THRESH_T5_V(HP_INT_THRESH_T5_M),
HP_INT_THRESH_T5_V(dbfifo_int_thresh));
}
t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_ENABLE_DROP,
F_ENABLE_DROP);
t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, ENABLE_DROP_F,
ENABLE_DROP_F);
/*
* SGE_FL_BUFFER_SIZE0 (RX_SMALL_PG_BUF) is set up by
@ -2905,15 +2905,15 @@ static int t4_sge_init_hard(struct adapter *adap)
THRESHOLD_1_V(s->counter_val[1]) |
THRESHOLD_2_V(s->counter_val[2]) |
THRESHOLD_3_V(s->counter_val[3]));
t4_write_reg(adap, SGE_TIMER_VALUE_0_AND_1,
TIMERVALUE0(us_to_core_ticks(adap, s->timer_val[0])) |
TIMERVALUE1(us_to_core_ticks(adap, s->timer_val[1])));
t4_write_reg(adap, SGE_TIMER_VALUE_2_AND_3,
TIMERVALUE2(us_to_core_ticks(adap, s->timer_val[2])) |
TIMERVALUE3(us_to_core_ticks(adap, s->timer_val[3])));
t4_write_reg(adap, SGE_TIMER_VALUE_4_AND_5,
TIMERVALUE4(us_to_core_ticks(adap, s->timer_val[4])) |
TIMERVALUE5(us_to_core_ticks(adap, s->timer_val[5])));
t4_write_reg(adap, SGE_TIMER_VALUE_0_AND_1_A,
TIMERVALUE0_V(us_to_core_ticks(adap, s->timer_val[0])) |
TIMERVALUE1_V(us_to_core_ticks(adap, s->timer_val[1])));
t4_write_reg(adap, SGE_TIMER_VALUE_2_AND_3_A,
TIMERVALUE2_V(us_to_core_ticks(adap, s->timer_val[2])) |
TIMERVALUE3_V(us_to_core_ticks(adap, s->timer_val[3])));
t4_write_reg(adap, SGE_TIMER_VALUE_4_AND_5_A,
TIMERVALUE4_V(us_to_core_ticks(adap, s->timer_val[4])) |
TIMERVALUE5_V(us_to_core_ticks(adap, s->timer_val[5])));
return 0;
}

224
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
View File

@ -150,20 +150,20 @@ void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
*/
void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
{
u32 req = ENABLE | FUNCTION(adap->fn) | reg;
u32 req = ENABLE_F | FUNCTION_V(adap->fn) | REGISTER_V(reg);
if (is_t4(adap->params.chip))
req |= F_LOCALCFG;
req |= LOCALCFG_F;
t4_write_reg(adap, PCIE_CFG_SPACE_REQ, req);
*val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA);
t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
*val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
/* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
* Configuration Space read. (None of the other fields matter when
* ENABLE is 0 so a simple register write is easier than a
* read-modify-write via t4_set_reg_field().)
*/
t4_write_reg(adap, PCIE_CFG_SPACE_REQ, 0);
t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
}
/*
@ -188,8 +188,8 @@ static void t4_report_fw_error(struct adapter *adap)
};
u32 pcie_fw;
pcie_fw = t4_read_reg(adap, MA_PCIE_FW);
if (pcie_fw & PCIE_FW_ERR)
pcie_fw = t4_read_reg(adap, PCIE_FW_A);
if (pcie_fw & PCIE_FW_ERR_F)
dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
reason[PCIE_FW_EVAL_G(pcie_fw)]);
}
@ -506,13 +506,13 @@ int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
* the address is relative to BAR0.
*/
mem_reg = t4_read_reg(adap,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
win));
mem_aperture = 1 << (GET_WINDOW(mem_reg) + 10);
mem_base = GET_PCIEOFST(mem_reg) << 10;
mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
if (is_t4(adap->params.chip))
mem_base -= adap->t4_bar0;
win_pf = is_t4(adap->params.chip) ? 0 : V_PFNUM(adap->fn);
win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->fn);
/* Calculate our initial PCI-E Memory Window Position and Offset into
* that Window.
@ -525,10 +525,10 @@ int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
* attempt to use the new value.)
*/
t4_write_reg(adap,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win),
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
pos | win_pf);
t4_read_reg(adap,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
/* Transfer data to/from the adapter as long as there's an integral
* number of 32-bit transfers to complete.
@ -553,11 +553,11 @@ int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
pos += mem_aperture;
offset = 0;
t4_write_reg(adap,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET,
win), pos | win_pf);
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
win), pos | win_pf);
t4_read_reg(adap,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET,
win));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
win));
}
}
@ -1366,95 +1366,97 @@ static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
static void pcie_intr_handler(struct adapter *adapter)
{
static const struct intr_info sysbus_intr_info[] = {
{ RNPP, "RXNP array parity error", -1, 1 },
{ RPCP, "RXPC array parity error", -1, 1 },
{ RCIP, "RXCIF array parity error", -1, 1 },
{ RCCP, "Rx completions control array parity error", -1, 1 },
{ RFTP, "RXFT array parity error", -1, 1 },
{ RNPP_F, "RXNP array parity error", -1, 1 },
{ RPCP_F, "RXPC array parity error", -1, 1 },
{ RCIP_F, "RXCIF array parity error", -1, 1 },
{ RCCP_F, "Rx completions control array parity error", -1, 1 },
{ RFTP_F, "RXFT array parity error", -1, 1 },
{ 0 }
};
static const struct intr_info pcie_port_intr_info[] = {
{ TPCP, "TXPC array parity error", -1, 1 },
{ TNPP, "TXNP array parity error", -1, 1 },
{ TFTP, "TXFT array parity error", -1, 1 },
{ TCAP, "TXCA array parity error", -1, 1 },
{ TCIP, "TXCIF array parity error", -1, 1 },
{ RCAP, "RXCA array parity error", -1, 1 },
{ OTDD, "outbound request TLP discarded", -1, 1 },
{ RDPE, "Rx data parity error", -1, 1 },
{ TDUE, "Tx uncorrectable data error", -1, 1 },
{ TPCP_F, "TXPC array parity error", -1, 1 },
{ TNPP_F, "TXNP array parity error", -1, 1 },
{ TFTP_F, "TXFT array parity error", -1, 1 },
{ TCAP_F, "TXCA array parity error", -1, 1 },
{ TCIP_F, "TXCIF array parity error", -1, 1 },
{ RCAP_F, "RXCA array parity error", -1, 1 },
{ OTDD_F, "outbound request TLP discarded", -1, 1 },
{ RDPE_F, "Rx data parity error", -1, 1 },
{ TDUE_F, "Tx uncorrectable data error", -1, 1 },
{ 0 }
};
static const struct intr_info pcie_intr_info[] = {
{ MSIADDRLPERR, "MSI AddrL parity error", -1, 1 },
{ MSIADDRHPERR, "MSI AddrH parity error", -1, 1 },
{ MSIDATAPERR, "MSI data parity error", -1, 1 },
{ MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
{ MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
{ MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
{ MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
{ PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 },
{ PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 },
{ TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
{ CCNTPERR, "PCI CMD channel count parity error", -1, 1 },
{ CREQPERR, "PCI CMD channel request parity error", -1, 1 },
{ CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
{ DCNTPERR, "PCI DMA channel count parity error", -1, 1 },
{ DREQPERR, "PCI DMA channel request parity error", -1, 1 },
{ DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
{ HCNTPERR, "PCI HMA channel count parity error", -1, 1 },
{ HREQPERR, "PCI HMA channel request parity error", -1, 1 },
{ HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
{ CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
{ FIDPERR, "PCI FID parity error", -1, 1 },
{ INTXCLRPERR, "PCI INTx clear parity error", -1, 1 },
{ MATAGPERR, "PCI MA tag parity error", -1, 1 },
{ PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
{ RXCPLPERR, "PCI Rx completion parity error", -1, 1 },
{ RXWRPERR, "PCI Rx write parity error", -1, 1 },
{ RPLPERR, "PCI replay buffer parity error", -1, 1 },
{ PCIESINT, "PCI core secondary fault", -1, 1 },
{ PCIEPINT, "PCI core primary fault", -1, 1 },
{ UNXSPLCPLERR, "PCI unexpected split completion error", -1, 0 },
{ MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
{ MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
{ MSIDATAPERR_F, "MSI data parity error", -1, 1 },
{ MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
{ MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
{ MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
{ MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
{ PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
{ PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
{ TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
{ CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
{ CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
{ CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
{ DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
{ DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
{ DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
{ HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
{ HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
{ HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
{ CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
{ FIDPERR_F, "PCI FID parity error", -1, 1 },
{ INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
{ MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
{ PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
{ RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
{ RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
{ RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
{ PCIESINT_F, "PCI core secondary fault", -1, 1 },
{ PCIEPINT_F, "PCI core primary fault", -1, 1 },
{ UNXSPLCPLERR_F, "PCI unexpected split completion error",
-1, 0 },
{ 0 }
};
static struct intr_info t5_pcie_intr_info[] = {
{ MSTGRPPERR, "Master Response Read Queue parity error",
{ MSTGRPPERR_F, "Master Response Read Queue parity error",
-1, 1 },
{ MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 },
{ MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 },
{ MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
{ MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
{ MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
{ MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
{ PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error",
{ MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
{ MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
{ MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
{ MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
{ MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
{ MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
{ PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
-1, 1 },
{ PIOREQGRPPERR, "PCI PIO request Group FIFO parity error",
{ PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
-1, 1 },
{ TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
{ MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 },
{ CREQPERR, "PCI CMD channel request parity error", -1, 1 },
{ CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
{ DREQWRPERR, "PCI DMA channel write request parity error",
{ TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
{ MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
{ CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
{ CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
{ DREQWRPERR_F, "PCI DMA channel write request parity error",
-1, 1 },
{ DREQPERR, "PCI DMA channel request parity error", -1, 1 },
{ DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
{ HREQWRPERR, "PCI HMA channel count parity error", -1, 1 },
{ HREQPERR, "PCI HMA channel request parity error", -1, 1 },
{ HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
{ CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
{ FIDPERR, "PCI FID parity error", -1, 1 },
{ VFIDPERR, "PCI INTx clear parity error", -1, 1 },
{ MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 },
{ PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
{ IPRXHDRGRPPERR, "PCI IP Rx header group parity error",
{ DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
{ DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
{ HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
{ HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
{ HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
{ CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
{ FIDPERR_F, "PCI FID parity error", -1, 1 },
{ VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
{ MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
{ PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
{ IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
-1, 1 },
{ IPRXDATAGRPPERR, "PCI IP Rx data group parity error", -1, 1 },
{ RPLPERR, "PCI IP replay buffer parity error", -1, 1 },
{ IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 },
{ TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 },
{ READRSPERR, "Outbound read error", -1, 0 },
{ IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
-1, 1 },
{ RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
{ IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
{ TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
{ READRSPERR_F, "Outbound read error", -1, 0 },
{ 0 }
};
@ -1462,15 +1464,15 @@ static void pcie_intr_handler(struct adapter *adapter)
if (is_t4(adapter->params.chip))
fat = t4_handle_intr_status(adapter,
PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
sysbus_intr_info) +
PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
sysbus_intr_info) +
t4_handle_intr_status(adapter,
PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
pcie_port_intr_info) +
t4_handle_intr_status(adapter, PCIE_INT_CAUSE,
PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
pcie_port_intr_info) +
t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
pcie_intr_info);
else
fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE,
fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
t5_pcie_intr_info);
if (fat)
@ -1590,7 +1592,7 @@ static void cim_intr_handler(struct adapter *adapter)
int fat;
if (t4_read_reg(adapter, MA_PCIE_FW) & PCIE_FW_ERR)
if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
t4_report_fw_error(adapter);
fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE,
@ -2750,9 +2752,9 @@ void t4_sge_decode_idma_state(struct adapter *adapter, int state)
"IDMA_FL_SEND_COMPLETION_TO_IMSG",
};
static const u32 sge_regs[] = {
SGE_DEBUG_DATA_LOW_INDEX_2,
SGE_DEBUG_DATA_LOW_INDEX_3,
SGE_DEBUG_DATA_HIGH_INDEX_10,
SGE_DEBUG_DATA_LOW_INDEX_2_A,
SGE_DEBUG_DATA_LOW_INDEX_3_A,
SGE_DEBUG_DATA_HIGH_INDEX_10_A,
};
const char **sge_idma_decode;
int sge_idma_decode_nstates;
@ -2819,7 +2821,7 @@ retry:
if (ret < 0) {
if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
goto retry;
if (t4_read_reg(adap, MA_PCIE_FW) & PCIE_FW_ERR)
if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
t4_report_fw_error(adap);
return ret;
}
@ -2869,8 +2871,8 @@ retry:
* timeout ... and then retry if we haven't exhausted
* our retries ...
*/
pcie_fw = t4_read_reg(adap, MA_PCIE_FW);
if (!(pcie_fw & (PCIE_FW_ERR|PCIE_FW_INIT))) {
pcie_fw = t4_read_reg(adap, PCIE_FW_A);
if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
if (waiting <= 0) {
if (retries-- > 0)
goto retry;
@ -2885,9 +2887,9 @@ retry:
* report errors preferentially.
*/
if (state) {
if (pcie_fw & PCIE_FW_ERR)
if (pcie_fw & PCIE_FW_ERR_F)
*state = DEV_STATE_ERR;
else if (pcie_fw & PCIE_FW_INIT)
else if (pcie_fw & PCIE_FW_INIT_F)
*state = DEV_STATE_INIT;
}
@ -2897,7 +2899,7 @@ retry:
* for our caller.
*/
if (master_mbox == PCIE_FW_MASTER_M &&
(pcie_fw & PCIE_FW_MASTER_VLD))
(pcie_fw & PCIE_FW_MASTER_VLD_F))
master_mbox = PCIE_FW_MASTER_G(pcie_fw);
break;
}
@ -3006,7 +3008,7 @@ static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
*/
if (ret == 0 || force) {
t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, UPCRST);
t4_set_reg_field(adap, PCIE_FW, PCIE_FW_HALT_F,
t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
PCIE_FW_HALT_F);
}
@ -3046,7 +3048,7 @@ static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
* doing it automatically, we need to clear the PCIE_FW.HALT
* bit.
*/
t4_set_reg_field(adap, PCIE_FW, PCIE_FW_HALT_F, 0);
t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
/*
* If we've been given a valid mailbox, first try to get the
@ -3070,7 +3072,7 @@ static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, 0);
for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
if (!(t4_read_reg(adap, PCIE_FW) & PCIE_FW_HALT_F))
if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
return 0;
msleep(100);
ms += 100;
@ -4146,7 +4148,7 @@ int t4_init_sge_params(struct adapter *adapter)
(QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->fn);
qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF);
qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
return 0;

573
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
View File

@ -369,196 +369,424 @@
#define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S)
#define ENABLE_DROP_F ENABLE_DROP_V(1U)
#define SGE_TIMER_VALUE_0_AND_1 0x10b8
#define TIMERVALUE0_MASK 0xffff0000U
#define TIMERVALUE0_SHIFT 16
#define TIMERVALUE0(x) ((x) << TIMERVALUE0_SHIFT)
#define TIMERVALUE0_GET(x) (((x) & TIMERVALUE0_MASK) >> TIMERVALUE0_SHIFT)
#define TIMERVALUE1_MASK 0x0000ffffU
#define TIMERVALUE1_SHIFT 0
#define TIMERVALUE1(x) ((x) << TIMERVALUE1_SHIFT)
#define TIMERVALUE1_GET(x) (((x) & TIMERVALUE1_MASK) >> TIMERVALUE1_SHIFT)
#define SGE_TIMER_VALUE_0_AND_1_A 0x10b8
#define SGE_TIMER_VALUE_2_AND_3 0x10bc
#define TIMERVALUE2_MASK 0xffff0000U
#define TIMERVALUE2_SHIFT 16
#define TIMERVALUE2(x) ((x) << TIMERVALUE2_SHIFT)
#define TIMERVALUE2_GET(x) (((x) & TIMERVALUE2_MASK) >> TIMERVALUE2_SHIFT)
#define TIMERVALUE3_MASK 0x0000ffffU
#define TIMERVALUE3_SHIFT 0
#define TIMERVALUE3(x) ((x) << TIMERVALUE3_SHIFT)
#define TIMERVALUE3_GET(x) (((x) & TIMERVALUE3_MASK) >> TIMERVALUE3_SHIFT)
#define TIMERVALUE0_S 16
#define TIMERVALUE0_M 0xffffU
#define TIMERVALUE0_V(x) ((x) << TIMERVALUE0_S)
#define TIMERVALUE0_G(x) (((x) >> TIMERVALUE0_S) & TIMERVALUE0_M)
#define SGE_TIMER_VALUE_4_AND_5 0x10c0
#define TIMERVALUE4_MASK 0xffff0000U
#define TIMERVALUE4_SHIFT 16
#define TIMERVALUE4(x) ((x) << TIMERVALUE4_SHIFT)
#define TIMERVALUE4_GET(x) (((x) & TIMERVALUE4_MASK) >> TIMERVALUE4_SHIFT)
#define TIMERVALUE5_MASK 0x0000ffffU
#define TIMERVALUE5_SHIFT 0
#define TIMERVALUE5(x) ((x) << TIMERVALUE5_SHIFT)
#define TIMERVALUE5_GET(x) (((x) & TIMERVALUE5_MASK) >> TIMERVALUE5_SHIFT)
#define TIMERVALUE1_S 0
#define TIMERVALUE1_M 0xffffU
#define TIMERVALUE1_V(x) ((x) << TIMERVALUE1_S)
#define TIMERVALUE1_G(x) (((x) >> TIMERVALUE1_S) & TIMERVALUE1_M)
#define SGE_DEBUG_INDEX 0x10cc
#define SGE_DEBUG_DATA_HIGH 0x10d0
#define SGE_DEBUG_DATA_LOW 0x10d4
#define SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8
#define SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
#define SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8
#define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
#define SGE_TIMER_VALUE_2_AND_3_A 0x10bc
#define TIMERVALUE2_S 16
#define TIMERVALUE2_M 0xffffU
#define TIMERVALUE2_V(x) ((x) << TIMERVALUE2_S)
#define TIMERVALUE2_G(x) (((x) >> TIMERVALUE2_S) & TIMERVALUE2_M)
#define TIMERVALUE3_S 0
#define TIMERVALUE3_M 0xffffU
#define TIMERVALUE3_V(x) ((x) << TIMERVALUE3_S)
#define TIMERVALUE3_G(x) (((x) >> TIMERVALUE3_S) & TIMERVALUE3_M)
#define SGE_TIMER_VALUE_4_AND_5_A 0x10c0
#define TIMERVALUE4_S 16
#define TIMERVALUE4_M 0xffffU
#define TIMERVALUE4_V(x) ((x) << TIMERVALUE4_S)
#define TIMERVALUE4_G(x) (((x) >> TIMERVALUE4_S) & TIMERVALUE4_M)
#define TIMERVALUE5_S 0
#define TIMERVALUE5_M 0xffffU
#define TIMERVALUE5_V(x) ((x) << TIMERVALUE5_S)
#define TIMERVALUE5_G(x) (((x) >> TIMERVALUE5_S) & TIMERVALUE5_M)
#define SGE_DEBUG_INDEX_A 0x10cc
#define SGE_DEBUG_DATA_HIGH_A 0x10d0
#define SGE_DEBUG_DATA_LOW_A 0x10d4
#define SGE_DEBUG_DATA_LOW_INDEX_2_A 0x12c8
#define SGE_DEBUG_DATA_LOW_INDEX_3_A 0x12cc
#define SGE_DEBUG_DATA_HIGH_INDEX_10_A 0x12a8
#define SGE_INGRESS_QUEUES_PER_PAGE_PF_A 0x10f4
#define SGE_INGRESS_QUEUES_PER_PAGE_VF_A 0x10f8
#define S_HP_INT_THRESH 28
#define M_HP_INT_THRESH 0xfU
#define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH)
#define S_LP_INT_THRESH_T5 18
#define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5)
#define M_LP_COUNT_T5 0x3ffffU
#define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT) & M_LP_COUNT_T5)
#define M_HP_COUNT 0x7ffU
#define S_HP_COUNT 16
#define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)
#define S_LP_INT_THRESH 12
#define M_LP_INT_THRESH 0xfU
#define M_LP_INT_THRESH_T5 0xfffU
#define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
#define M_LP_COUNT 0x7ffU
#define S_LP_COUNT 0
#define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
#define A_SGE_DBFIFO_STATUS 0x10a4
#define HP_INT_THRESH_S 28
#define HP_INT_THRESH_M 0xfU
#define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)
#define SGE_STAT_TOTAL 0x10e4
#define SGE_STAT_MATCH 0x10e8
#define HP_COUNT_S 16
#define HP_COUNT_M 0x7ffU
#define HP_COUNT_G(x) (((x) >> HP_COUNT_S) & HP_COUNT_M)
#define SGE_STAT_CFG 0x10ec
#define S_STATSOURCE_T5 9
#define STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
#define LP_INT_THRESH_S 12
#define LP_INT_THRESH_M 0xfU
#define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S)
#define SGE_DBFIFO_STATUS2 0x1118
#define M_HP_COUNT_T5 0x3ffU
#define G_HP_COUNT_T5(x) ((x) & M_HP_COUNT_T5)
#define S_HP_INT_THRESH_T5 10
#define M_HP_INT_THRESH_T5 0xfU
#define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5)
#define LP_COUNT_S 0
#define LP_COUNT_M 0x7ffU
#define LP_COUNT_G(x) (((x) >> LP_COUNT_S) & LP_COUNT_M)
#define S_ENABLE_DROP 13
#define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP)
#define F_ENABLE_DROP V_ENABLE_DROP(1U)
#define S_DROPPED_DB 0
#define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
#define F_DROPPED_DB V_DROPPED_DB(1U)
#define A_SGE_DOORBELL_CONTROL 0x10a8
#define LP_INT_THRESH_T5_S 18
#define LP_INT_THRESH_T5_M 0xfffU
#define LP_INT_THRESH_T5_V(x) ((x) << LP_INT_THRESH_T5_S)
#define A_SGE_CTXT_CMD 0x11fc
#define A_SGE_DBQ_CTXT_BADDR 0x1084
#define LP_COUNT_T5_S 0
#define LP_COUNT_T5_M 0x3ffffU
#define LP_COUNT_T5_G(x) (((x) >> LP_COUNT_T5_S) & LP_COUNT_T5_M)
#define PCIE_PF_CFG 0x40
#define AIVEC(x) ((x) << 4)
#define AIVEC_MASK 0x3ffU
#define SGE_DOORBELL_CONTROL_A 0x10a8
#define PCIE_PF_CLI 0x44
#define PCIE_INT_CAUSE 0x3004
#define UNXSPLCPLERR 0x20000000U
#define PCIEPINT 0x10000000U
#define PCIESINT 0x08000000U
#define RPLPERR 0x04000000U
#define RXWRPERR 0x02000000U
#define RXCPLPERR 0x01000000U
#define PIOTAGPERR 0x00800000U
#define MATAGPERR 0x00400000U
#define INTXCLRPERR 0x00200000U
#define FIDPERR 0x00100000U
#define CFGSNPPERR 0x00080000U
#define HRSPPERR 0x00040000U
#define HREQPERR 0x00020000U
#define HCNTPERR 0x00010000U
#define DRSPPERR 0x00008000U
#define DREQPERR 0x00004000U
#define DCNTPERR 0x00002000U
#define CRSPPERR 0x00001000U
#define CREQPERR 0x00000800U
#define CCNTPERR 0x00000400U
#define TARTAGPERR 0x00000200U
#define PIOREQPERR 0x00000100U
#define PIOCPLPERR 0x00000080U
#define MSIXDIPERR 0x00000040U
#define MSIXDATAPERR 0x00000020U
#define MSIXADDRHPERR 0x00000010U
#define MSIXADDRLPERR 0x00000008U
#define MSIDATAPERR 0x00000004U
#define MSIADDRHPERR 0x00000002U
#define MSIADDRLPERR 0x00000001U
#define SGE_STAT_TOTAL_A 0x10e4
#define SGE_STAT_MATCH_A 0x10e8
#define SGE_STAT_CFG_A 0x10ec
#define READRSPERR 0x20000000U
#define TRGT1GRPPERR 0x10000000U
#define IPSOTPERR 0x08000000U
#define IPRXDATAGRPPERR 0x02000000U
#define IPRXHDRGRPPERR 0x01000000U
#define MAGRPPERR 0x00400000U
#define VFIDPERR 0x00200000U
#define HREQWRPERR 0x00010000U
#define DREQWRPERR 0x00002000U
#define MSTTAGQPERR 0x00000400U
#define PIOREQGRPPERR 0x00000100U
#define PIOCPLGRPPERR 0x00000080U
#define MSIXSTIPERR 0x00000004U
#define MSTTIMEOUTPERR 0x00000002U
#define MSTGRPPERR 0x00000001U
#define STATSOURCE_T5_S 9
#define STATSOURCE_T5_V(x) ((x) << STATSOURCE_T5_S)
#define PCIE_NONFAT_ERR 0x3010
#define PCIE_CFG_SPACE_REQ 0x3060
#define PCIE_CFG_SPACE_DATA 0x3064
#define PCIE_MEM_ACCESS_BASE_WIN 0x3068
#define S_PCIEOFST 10
#define M_PCIEOFST 0x3fffffU
#define GET_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST)
#define PCIEOFST_MASK 0xfffffc00U
#define BIR_MASK 0x00000300U
#define BIR_SHIFT 8
#define BIR(x) ((x) << BIR_SHIFT)
#define WINDOW_MASK 0x000000ffU
#define WINDOW_SHIFT 0
#define WINDOW(x) ((x) << WINDOW_SHIFT)
#define GET_WINDOW(x) (((x) >> WINDOW_SHIFT) & WINDOW_MASK)
#define PCIE_MEM_ACCESS_OFFSET 0x306c
#define ENABLE (1U << 30)
#define FUNCTION(x) ((x) << 12)
#define F_LOCALCFG (1U << 28)
#define SGE_DBFIFO_STATUS2_A 0x1118
#define S_PFNUM 0
#define V_PFNUM(x) ((x) << S_PFNUM)
#define HP_INT_THRESH_T5_S 10
#define HP_INT_THRESH_T5_M 0xfU
#define HP_INT_THRESH_T5_V(x) ((x) << HP_INT_THRESH_T5_S)
#define PCIE_FW 0x30b8
#define PCIE_FW_ERR 0x80000000U
#define PCIE_FW_INIT 0x40000000U
#define PCIE_FW_HALT 0x20000000U
#define PCIE_FW_MASTER_VLD 0x00008000U
#define PCIE_FW_MASTER(x) ((x) << 12)
#define PCIE_FW_MASTER_MASK 0x7
#define PCIE_FW_MASTER_GET(x) (((x) >> 12) & PCIE_FW_MASTER_MASK)
#define HP_COUNT_T5_S 0
#define HP_COUNT_T5_M 0x3ffU
#define HP_COUNT_T5_G(x) (((x) >> HP_COUNT_T5_S) & HP_COUNT_T5_M)
#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908
#define RNPP 0x80000000U
#define RPCP 0x20000000U
#define RCIP 0x08000000U
#define RCCP 0x04000000U
#define RFTP 0x00800000U
#define PTRP 0x00100000U
#define ENABLE_DROP_S 13
#define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S)
#define ENABLE_DROP_F ENABLE_DROP_V(1U)
#define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4
#define TPCP 0x40000000U
#define TNPP 0x20000000U
#define TFTP 0x10000000U
#define TCAP 0x08000000U
#define TCIP 0x04000000U
#define RCAP 0x02000000U
#define PLUP 0x00800000U
#define PLDN 0x00400000U
#define OTDD 0x00200000U
#define GTRP 0x00100000U
#define RDPE 0x00040000U
#define TDCE 0x00020000U
#define TDUE 0x00010000U
#define DROPPED_DB_S 0
#define DROPPED_DB_V(x) ((x) << DROPPED_DB_S)
#define DROPPED_DB_F DROPPED_DB_V(1U)
#define SGE_CTXT_CMD_A 0x11fc
#define SGE_DBQ_CTXT_BADDR_A 0x1084
/* registers for module PCIE */
#define PCIE_PF_CFG_A 0x40
#define AIVEC_S 4
#define AIVEC_M 0x3ffU
#define AIVEC_V(x) ((x) << AIVEC_S)
#define PCIE_PF_CLI_A 0x44
#define PCIE_INT_CAUSE_A 0x3004
#define UNXSPLCPLERR_S 29
#define UNXSPLCPLERR_V(x) ((x) << UNXSPLCPLERR_S)
#define UNXSPLCPLERR_F UNXSPLCPLERR_V(1U)
#define PCIEPINT_S 28
#define PCIEPINT_V(x) ((x) << PCIEPINT_S)
#define PCIEPINT_F PCIEPINT_V(1U)
#define PCIESINT_S 27
#define PCIESINT_V(x) ((x) << PCIESINT_S)
#define PCIESINT_F PCIESINT_V(1U)
#define RPLPERR_S 26
#define RPLPERR_V(x) ((x) << RPLPERR_S)
#define RPLPERR_F RPLPERR_V(1U)
#define RXWRPERR_S 25
#define RXWRPERR_V(x) ((x) << RXWRPERR_S)
#define RXWRPERR_F RXWRPERR_V(1U)
#define RXCPLPERR_S 24
#define RXCPLPERR_V(x) ((x) << RXCPLPERR_S)
#define RXCPLPERR_F RXCPLPERR_V(1U)
#define PIOTAGPERR_S 23
#define PIOTAGPERR_V(x) ((x) << PIOTAGPERR_S)
#define PIOTAGPERR_F PIOTAGPERR_V(1U)
#define MATAGPERR_S 22
#define MATAGPERR_V(x) ((x) << MATAGPERR_S)
#define MATAGPERR_F MATAGPERR_V(1U)
#define INTXCLRPERR_S 21
#define INTXCLRPERR_V(x) ((x) << INTXCLRPERR_S)
#define INTXCLRPERR_F INTXCLRPERR_V(1U)
#define FIDPERR_S 20
#define FIDPERR_V(x) ((x) << FIDPERR_S)
#define FIDPERR_F FIDPERR_V(1U)
#define CFGSNPPERR_S 19
#define CFGSNPPERR_V(x) ((x) << CFGSNPPERR_S)
#define CFGSNPPERR_F CFGSNPPERR_V(1U)
#define HRSPPERR_S 18
#define HRSPPERR_V(x) ((x) << HRSPPERR_S)
#define HRSPPERR_F HRSPPERR_V(1U)
#define HREQPERR_S 17
#define HREQPERR_V(x) ((x) << HREQPERR_S)
#define HREQPERR_F HREQPERR_V(1U)
#define HCNTPERR_S 16
#define HCNTPERR_V(x) ((x) << HCNTPERR_S)
#define HCNTPERR_F HCNTPERR_V(1U)
#define DRSPPERR_S 15
#define DRSPPERR_V(x) ((x) << DRSPPERR_S)
#define DRSPPERR_F DRSPPERR_V(1U)
#define DREQPERR_S 14
#define DREQPERR_V(x) ((x) << DREQPERR_S)
#define DREQPERR_F DREQPERR_V(1U)
#define DCNTPERR_S 13
#define DCNTPERR_V(x) ((x) << DCNTPERR_S)
#define DCNTPERR_F DCNTPERR_V(1U)
#define CRSPPERR_S 12
#define CRSPPERR_V(x) ((x) << CRSPPERR_S)
#define CRSPPERR_F CRSPPERR_V(1U)
#define CREQPERR_S 11
#define CREQPERR_V(x) ((x) << CREQPERR_S)
#define CREQPERR_F CREQPERR_V(1U)
#define CCNTPERR_S 10
#define CCNTPERR_V(x) ((x) << CCNTPERR_S)
#define CCNTPERR_F CCNTPERR_V(1U)
#define TARTAGPERR_S 9
#define TARTAGPERR_V(x) ((x) << TARTAGPERR_S)
#define TARTAGPERR_F TARTAGPERR_V(1U)
#define PIOREQPERR_S 8
#define PIOREQPERR_V(x) ((x) << PIOREQPERR_S)
#define PIOREQPERR_F PIOREQPERR_V(1U)
#define PIOCPLPERR_S 7
#define PIOCPLPERR_V(x) ((x) << PIOCPLPERR_S)
#define PIOCPLPERR_F PIOCPLPERR_V(1U)
#define MSIXDIPERR_S 6
#define MSIXDIPERR_V(x) ((x) << MSIXDIPERR_S)
#define MSIXDIPERR_F MSIXDIPERR_V(1U)
#define MSIXDATAPERR_S 5
#define MSIXDATAPERR_V(x) ((x) << MSIXDATAPERR_S)
#define MSIXDATAPERR_F MSIXDATAPERR_V(1U)
#define MSIXADDRHPERR_S 4
#define MSIXADDRHPERR_V(x) ((x) << MSIXADDRHPERR_S)
#define MSIXADDRHPERR_F MSIXADDRHPERR_V(1U)
#define MSIXADDRLPERR_S 3
#define MSIXADDRLPERR_V(x) ((x) << MSIXADDRLPERR_S)
#define MSIXADDRLPERR_F MSIXADDRLPERR_V(1U)
#define MSIDATAPERR_S 2
#define MSIDATAPERR_V(x) ((x) << MSIDATAPERR_S)
#define MSIDATAPERR_F MSIDATAPERR_V(1U)
#define MSIADDRHPERR_S 1
#define MSIADDRHPERR_V(x) ((x) << MSIADDRHPERR_S)
#define MSIADDRHPERR_F MSIADDRHPERR_V(1U)
#define MSIADDRLPERR_S 0
#define MSIADDRLPERR_V(x) ((x) << MSIADDRLPERR_S)
#define MSIADDRLPERR_F MSIADDRLPERR_V(1U)
#define READRSPERR_S 29
#define READRSPERR_V(x) ((x) << READRSPERR_S)
#define READRSPERR_F READRSPERR_V(1U)
#define TRGT1GRPPERR_S 28
#define TRGT1GRPPERR_V(x) ((x) << TRGT1GRPPERR_S)
#define TRGT1GRPPERR_F TRGT1GRPPERR_V(1U)
#define IPSOTPERR_S 27
#define IPSOTPERR_V(x) ((x) << IPSOTPERR_S)
#define IPSOTPERR_F IPSOTPERR_V(1U)
#define IPRETRYPERR_S 26
#define IPRETRYPERR_V(x) ((x) << IPRETRYPERR_S)
#define IPRETRYPERR_F IPRETRYPERR_V(1U)
#define IPRXDATAGRPPERR_S 25
#define IPRXDATAGRPPERR_V(x) ((x) << IPRXDATAGRPPERR_S)
#define IPRXDATAGRPPERR_F IPRXDATAGRPPERR_V(1U)
#define IPRXHDRGRPPERR_S 24
#define IPRXHDRGRPPERR_V(x) ((x) << IPRXHDRGRPPERR_S)
#define IPRXHDRGRPPERR_F IPRXHDRGRPPERR_V(1U)
#define MAGRPPERR_S 22
#define MAGRPPERR_V(x) ((x) << MAGRPPERR_S)
#define MAGRPPERR_F MAGRPPERR_V(1U)
#define VFIDPERR_S 21
#define VFIDPERR_V(x) ((x) << VFIDPERR_S)
#define VFIDPERR_F VFIDPERR_V(1U)
#define HREQWRPERR_S 16
#define HREQWRPERR_V(x) ((x) << HREQWRPERR_S)
#define HREQWRPERR_F HREQWRPERR_V(1U)
#define DREQWRPERR_S 13
#define DREQWRPERR_V(x) ((x) << DREQWRPERR_S)
#define DREQWRPERR_F DREQWRPERR_V(1U)
#define CREQRDPERR_S 11
#define CREQRDPERR_V(x) ((x) << CREQRDPERR_S)
#define CREQRDPERR_F CREQRDPERR_V(1U)
#define MSTTAGQPERR_S 10
#define MSTTAGQPERR_V(x) ((x) << MSTTAGQPERR_S)
#define MSTTAGQPERR_F MSTTAGQPERR_V(1U)
#define PIOREQGRPPERR_S 8
#define PIOREQGRPPERR_V(x) ((x) << PIOREQGRPPERR_S)
#define PIOREQGRPPERR_F PIOREQGRPPERR_V(1U)
#define PIOCPLGRPPERR_S 7
#define PIOCPLGRPPERR_V(x) ((x) << PIOCPLGRPPERR_S)
#define PIOCPLGRPPERR_F PIOCPLGRPPERR_V(1U)
#define MSIXSTIPERR_S 2
#define MSIXSTIPERR_V(x) ((x) << MSIXSTIPERR_S)
#define MSIXSTIPERR_F MSIXSTIPERR_V(1U)
#define MSTTIMEOUTPERR_S 1
#define MSTTIMEOUTPERR_V(x) ((x) << MSTTIMEOUTPERR_S)
#define MSTTIMEOUTPERR_F MSTTIMEOUTPERR_V(1U)
#define MSTGRPPERR_S 0
#define MSTGRPPERR_V(x) ((x) << MSTGRPPERR_S)
#define MSTGRPPERR_F MSTGRPPERR_V(1U)
#define PCIE_NONFAT_ERR_A 0x3010
#define PCIE_CFG_SPACE_REQ_A 0x3060
#define PCIE_CFG_SPACE_DATA_A 0x3064
#define PCIE_MEM_ACCESS_BASE_WIN_A 0x3068
#define PCIEOFST_S 10
#define PCIEOFST_M 0x3fffffU
#define PCIEOFST_G(x) (((x) >> PCIEOFST_S) & PCIEOFST_M)
#define BIR_S 8
#define BIR_M 0x3U
#define BIR_V(x) ((x) << BIR_S)
#define BIR_G(x) (((x) >> BIR_S) & BIR_M)
#define WINDOW_S 0
#define WINDOW_M 0xffU
#define WINDOW_V(x) ((x) << WINDOW_S)
#define WINDOW_G(x) (((x) >> WINDOW_S) & WINDOW_M)
#define PCIE_MEM_ACCESS_OFFSET_A 0x306c
#define ENABLE_S 30
#define ENABLE_V(x) ((x) << ENABLE_S)
#define ENABLE_F ENABLE_V(1U)
#define LOCALCFG_S 28
#define LOCALCFG_V(x) ((x) << LOCALCFG_S)
#define LOCALCFG_F LOCALCFG_V(1U)
#define FUNCTION_S 12
#define FUNCTION_V(x) ((x) << FUNCTION_S)
#define REGISTER_S 0
#define REGISTER_V(x) ((x) << REGISTER_S)
#define PFNUM_S 0
#define PFNUM_V(x) ((x) << PFNUM_S)
#define PCIE_FW_A 0x30b8
#define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A 0x5908
#define RNPP_S 31
#define RNPP_V(x) ((x) << RNPP_S)
#define RNPP_F RNPP_V(1U)
#define RPCP_S 29
#define RPCP_V(x) ((x) << RPCP_S)
#define RPCP_F RPCP_V(1U)
#define RCIP_S 27
#define RCIP_V(x) ((x) << RCIP_S)
#define RCIP_F RCIP_V(1U)
#define RCCP_S 26
#define RCCP_V(x) ((x) << RCCP_S)
#define RCCP_F RCCP_V(1U)
#define RFTP_S 23
#define RFTP_V(x) ((x) << RFTP_S)
#define RFTP_F RFTP_V(1U)
#define PTRP_S 20
#define PTRP_V(x) ((x) << PTRP_S)
#define PTRP_F PTRP_V(1U)
#define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A 0x59a4
#define TPCP_S 30
#define TPCP_V(x) ((x) << TPCP_S)
#define TPCP_F TPCP_V(1U)
#define TNPP_S 29
#define TNPP_V(x) ((x) << TNPP_S)
#define TNPP_F TNPP_V(1U)
#define TFTP_S 28
#define TFTP_V(x) ((x) << TFTP_S)
#define TFTP_F TFTP_V(1U)
#define TCAP_S 27
#define TCAP_V(x) ((x) << TCAP_S)
#define TCAP_F TCAP_V(1U)
#define TCIP_S 26
#define TCIP_V(x) ((x) << TCIP_S)
#define TCIP_F TCIP_V(1U)
#define RCAP_S 25
#define RCAP_V(x) ((x) << RCAP_S)
#define RCAP_F RCAP_V(1U)
#define PLUP_S 23
#define PLUP_V(x) ((x) << PLUP_S)
#define PLUP_F PLUP_V(1U)
#define PLDN_S 22
#define PLDN_V(x) ((x) << PLDN_S)
#define PLDN_F PLDN_V(1U)
#define OTDD_S 21
#define OTDD_V(x) ((x) << OTDD_S)
#define OTDD_F OTDD_V(1U)
#define GTRP_S 20
#define GTRP_V(x) ((x) << GTRP_S)
#define GTRP_F GTRP_V(1U)
#define RDPE_S 18
#define RDPE_V(x) ((x) << RDPE_S)
#define RDPE_F RDPE_V(1U)
#define TDCE_S 17
#define TDCE_V(x) ((x) << TDCE_S)
#define TDCE_F TDCE_V(1U)
#define TDUE_S 16
#define TDUE_V(x) ((x) << TDUE_S)
#define TDUE_F TDUE_V(1U)
#define MC_INT_CAUSE 0x7518
#define MC_P_INT_CAUSE 0x41318
@ -663,7 +891,6 @@
#define MEM_WRAP_CLIENT_NUM_MASK 0x0000000fU
#define MEM_WRAP_CLIENT_NUM_SHIFT 0
#define MEM_WRAP_CLIENT_NUM_GET(x) (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT)
#define MA_PCIE_FW 0x30b8
#define MA_PARITY_ERROR_STATUS 0x77f4
#define MA_PARITY_ERROR_STATUS2 0x7804

4
drivers/net/ethernet/chelsio/cxgb4/t4_values.h
View File

@ -78,4 +78,8 @@
#define SGE_UDB_GTS 20
#define SGE_UDB_WCDOORBELL 64
/* PCI-E definitions */
#define WINDOW_SHIFT_X 10
#define PCIEOFST_SHIFT_X 10
#endif /* __T4_VALUES_H__ */

12
drivers/net/ethernet/chelsio/cxgb4vf/cxgb4vf_main.c
View File

@ -2294,17 +2294,17 @@ static int adap_init0(struct adapter *adapter)
* threshold values from the SGE parameters.
*/
s->timer_val[0] = core_ticks_to_us(adapter,
TIMERVALUE0_GET(sge_params->sge_timer_value_0_and_1));
TIMERVALUE0_G(sge_params->sge_timer_value_0_and_1));
s->timer_val[1] = core_ticks_to_us(adapter,
TIMERVALUE1_GET(sge_params->sge_timer_value_0_and_1));
TIMERVALUE1_G(sge_params->sge_timer_value_0_and_1));
s->timer_val[2] = core_ticks_to_us(adapter,
TIMERVALUE0_GET(sge_params->sge_timer_value_2_and_3));
TIMERVALUE0_G(sge_params->sge_timer_value_2_and_3));
s->timer_val[3] = core_ticks_to_us(adapter,
TIMERVALUE1_GET(sge_params->sge_timer_value_2_and_3));
TIMERVALUE1_G(sge_params->sge_timer_value_2_and_3));
s->timer_val[4] = core_ticks_to_us(adapter,
TIMERVALUE0_GET(sge_params->sge_timer_value_4_and_5));
TIMERVALUE0_G(sge_params->sge_timer_value_4_and_5));
s->timer_val[5] = core_ticks_to_us(adapter,
TIMERVALUE1_GET(sge_params->sge_timer_value_4_and_5));
TIMERVALUE1_G(sge_params->sge_timer_value_4_and_5));
s->counter_val[0] = THRESHOLD_0_G(sge_params->sge_ingress_rx_threshold);
s->counter_val[1] = THRESHOLD_1_G(sge_params->sge_ingress_rx_threshold);

6
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_hw.c
View File

@ -537,11 +537,11 @@ int t4vf_get_sge_params(struct adapter *adapter)
params[3] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_FL_BUFFER_SIZE1_A));
params[4] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_0_AND_1));
FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_0_AND_1_A));
params[5] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_2_AND_3));
FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_2_AND_3_A));
params[6] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_REG) |
FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_4_AND_5));
FW_PARAMS_PARAM_XYZ_V(SGE_TIMER_VALUE_4_AND_5_A));
v = t4vf_query_params(adapter, 7, params, vals);
if (v)
return v;

33
drivers/scsi/csiostor/csio_hw.c
View File

@ -959,8 +959,8 @@ retry:
* timeout ... and then retry if we haven't exhausted
* our retries ...
*/
pcie_fw = csio_rd_reg32(hw, PCIE_FW);
if (!(pcie_fw & (PCIE_FW_ERR|PCIE_FW_INIT))) {
pcie_fw = csio_rd_reg32(hw, PCIE_FW_A);
if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
if (waiting <= 0) {
if (retries-- > 0)
goto retry;
@ -976,10 +976,10 @@ retry:
* report errors preferentially.
*/
if (state) {
if (pcie_fw & PCIE_FW_ERR) {
if (pcie_fw & PCIE_FW_ERR_F) {
*state = CSIO_DEV_STATE_ERR;
rv = -ETIMEDOUT;
} else if (pcie_fw & PCIE_FW_INIT)
} else if (pcie_fw & PCIE_FW_INIT_F)
*state = CSIO_DEV_STATE_INIT;
}
@ -988,9 +988,9 @@ retry:
* there's not a valid Master PF, grab its identity
* for our caller.
*/
if (mpfn == PCIE_FW_MASTER_MASK &&
(pcie_fw & PCIE_FW_MASTER_VLD))
mpfn = PCIE_FW_MASTER_GET(pcie_fw);
if (mpfn == PCIE_FW_MASTER_M &&
(pcie_fw & PCIE_FW_MASTER_VLD_F))
mpfn = PCIE_FW_MASTER_G(pcie_fw);
break;
}
hw->flags &= ~CSIO_HWF_MASTER;
@ -1156,7 +1156,7 @@ csio_hw_fw_halt(struct csio_hw *hw, uint32_t mbox, int32_t force)
* If a legitimate mailbox is provided, issue a RESET command
* with a HALT indication.
*/
if (mbox <= PCIE_FW_MASTER_MASK) {
if (mbox <= PCIE_FW_MASTER_M) {
struct csio_mb *mbp;
mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
@ -1194,7 +1194,8 @@ csio_hw_fw_halt(struct csio_hw *hw, uint32_t mbox, int32_t force)
*/
if (retval == 0 || force) {
csio_set_reg_field(hw, CIM_BOOT_CFG, UPCRST, UPCRST);
csio_set_reg_field(hw, PCIE_FW, PCIE_FW_HALT, PCIE_FW_HALT);
csio_set_reg_field(hw, PCIE_FW_A, PCIE_FW_HALT_F,
PCIE_FW_HALT_F);
}
/*
@ -1234,7 +1235,7 @@ csio_hw_fw_restart(struct csio_hw *hw, uint32_t mbox, int32_t reset)
* doing it automatically, we need to clear the PCIE_FW.HALT
* bit.
*/
csio_set_reg_field(hw, PCIE_FW, PCIE_FW_HALT, 0);
csio_set_reg_field(hw, PCIE_FW_A, PCIE_FW_HALT_F, 0);
/*
* If we've been given a valid mailbox, first try to get the
@ -1243,7 +1244,7 @@ csio_hw_fw_restart(struct csio_hw *hw, uint32_t mbox, int32_t reset)
* valid mailbox or the RESET command failed, fall back to
* hitting the chip with a hammer.
*/
if (mbox <= PCIE_FW_MASTER_MASK) {
if (mbox <= PCIE_FW_MASTER_M) {
csio_set_reg_field(hw, CIM_BOOT_CFG, UPCRST, 0);
msleep(100);
if (csio_do_reset(hw, true) == 0)
@ -1257,7 +1258,7 @@ csio_hw_fw_restart(struct csio_hw *hw, uint32_t mbox, int32_t reset)
csio_set_reg_field(hw, CIM_BOOT_CFG, UPCRST, 0);
for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
if (!(csio_rd_reg32(hw, PCIE_FW) & PCIE_FW_HALT))
if (!(csio_rd_reg32(hw, PCIE_FW_A) & PCIE_FW_HALT_F))
return 0;
msleep(100);
ms += 100;
@ -2237,11 +2238,11 @@ csio_hw_intr_enable(struct csio_hw *hw)
* by FW, so do nothing for INTX.
*/
if (hw->intr_mode == CSIO_IM_MSIX)
csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG),
AIVEC(AIVEC_MASK), vec);
csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG_A),
AIVEC_V(AIVEC_M), vec);
else if (hw->intr_mode == CSIO_IM_MSI)
csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG),
AIVEC(AIVEC_MASK), 0);
csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG_A),
AIVEC_V(AIVEC_M), 0);
csio_wr_reg32(hw, PF_INTR_MASK, MYPF_REG(PL_PF_INT_ENABLE));

4
drivers/scsi/csiostor/csio_hw_chip.h
View File

@ -71,10 +71,10 @@ static inline int csio_is_t5(uint16_t chip)
#define CSIO_HW_LP_INT_THRESH(hw, val) \
(csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_V(val)) : \
(V_LP_INT_THRESH_T5(val)))
(LP_INT_THRESH_T5_V(val)))
#define CSIO_HW_M_LP_INT_THRESH(hw) \
(csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_M) : (M_LP_INT_THRESH_T5))
(csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_M) : (LP_INT_THRESH_T5_M))
#define CSIO_MAC_INT_CAUSE_REG(hw, port) \
(csio_is_t4(hw->chip_id) ? (PORT_REG(port, XGMAC_PORT_INT_CAUSE)) : \

112
drivers/scsi/csiostor/csio_hw_t4.c
View File

@ -96,11 +96,11 @@ csio_t4_set_mem_win(struct csio_hw *hw, uint32_t win)
* back MA register to ensure that changes propagate before we attempt
* to use the new values.)
*/
csio_wr_reg32(hw, mem_win_base | BIR(0) |
WINDOW(ilog2(MEMWIN_APERTURE) - 10),
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
csio_wr_reg32(hw, mem_win_base | BIR_V(0) |
WINDOW_V(ilog2(MEMWIN_APERTURE) - 10),
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
csio_rd_reg32(hw,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
return 0;
}
@ -111,69 +111,69 @@ static void
csio_t4_pcie_intr_handler(struct csio_hw *hw)
{
static struct intr_info sysbus_intr_info[] = {
{ RNPP, "RXNP array parity error", -1, 1 },
{ RPCP, "RXPC array parity error", -1, 1 },
{ RCIP, "RXCIF array parity error", -1, 1 },
{ RCCP, "Rx completions control array parity error", -1, 1 },
{ RFTP, "RXFT array parity error", -1, 1 },
{ RNPP_F, "RXNP array parity error", -1, 1 },
{ RPCP_F, "RXPC array parity error", -1, 1 },
{ RCIP_F, "RXCIF array parity error", -1, 1 },
{ RCCP_F, "Rx completions control array parity error", -1, 1 },
{ RFTP_F, "RXFT array parity error", -1, 1 },
{ 0, NULL, 0, 0 }
};
static struct intr_info pcie_port_intr_info[] = {
{ TPCP, "TXPC array parity error", -1, 1 },
{ TNPP, "TXNP array parity error", -1, 1 },
{ TFTP, "TXFT array parity error", -1, 1 },
{ TCAP, "TXCA array parity error", -1, 1 },
{ TCIP, "TXCIF array parity error", -1, 1 },
{ RCAP, "RXCA array parity error", -1, 1 },
{ OTDD, "outbound request TLP discarded", -1, 1 },
{ RDPE, "Rx data parity error", -1, 1 },
{ TDUE, "Tx uncorrectable data error", -1, 1 },
{ TPCP_F, "TXPC array parity error", -1, 1 },
{ TNPP_F, "TXNP array parity error", -1, 1 },
{ TFTP_F, "TXFT array parity error", -1, 1 },
{ TCAP_F, "TXCA array parity error", -1, 1 },
{ TCIP_F, "TXCIF array parity error", -1, 1 },
{ RCAP_F, "RXCA array parity error", -1, 1 },
{ OTDD_F, "outbound request TLP discarded", -1, 1 },
{ RDPE_F, "Rx data parity error", -1, 1 },
{ TDUE_F, "Tx uncorrectable data error", -1, 1 },
{ 0, NULL, 0, 0 }
};
static struct intr_info pcie_intr_info[] = {
{ MSIADDRLPERR, "MSI AddrL parity error", -1, 1 },
{ MSIADDRHPERR, "MSI AddrH parity error", -1, 1 },
{ MSIDATAPERR, "MSI data parity error", -1, 1 },
{ MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
{ MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
{ MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
{ MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
{ PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 },
{ PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 },
{ TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
{ CCNTPERR, "PCI CMD channel count parity error", -1, 1 },
{ CREQPERR, "PCI CMD channel request parity error", -1, 1 },
{ CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
{ DCNTPERR, "PCI DMA channel count parity error", -1, 1 },
{ DREQPERR, "PCI DMA channel request parity error", -1, 1 },
{ DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
{ HCNTPERR, "PCI HMA channel count parity error", -1, 1 },
{ HREQPERR, "PCI HMA channel request parity error", -1, 1 },
{ HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
{ CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
{ FIDPERR, "PCI FID parity error", -1, 1 },
{ INTXCLRPERR, "PCI INTx clear parity error", -1, 1 },
{ MATAGPERR, "PCI MA tag parity error", -1, 1 },
{ PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
{ RXCPLPERR, "PCI Rx completion parity error", -1, 1 },
{ RXWRPERR, "PCI Rx write parity error", -1, 1 },
{ RPLPERR, "PCI replay buffer parity error", -1, 1 },
{ PCIESINT, "PCI core secondary fault", -1, 1 },
{ PCIEPINT, "PCI core primary fault", -1, 1 },
{ UNXSPLCPLERR, "PCI unexpected split completion error", -1,
{ MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
{ MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
{ MSIDATAPERR_F, "MSI data parity error", -1, 1 },
{ MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
{ MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
{ MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
{ MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
{ PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
{ PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
{ TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
{ CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
{ CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
{ CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
{ DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
{ DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
{ DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
{ HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
{ HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
{ HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
{ CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
{ FIDPERR_F, "PCI FID parity error", -1, 1 },
{ INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
{ MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
{ PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
{ RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
{ RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
{ RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
{ PCIESINT_F, "PCI core secondary fault", -1, 1 },
{ PCIEPINT_F, "PCI core primary fault", -1, 1 },
{ UNXSPLCPLERR_F, "PCI unexpected split completion error", -1,
0 },
{ 0, NULL, 0, 0 }
};
int fat;
fat = csio_handle_intr_status(hw,
PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
sysbus_intr_info) +
csio_handle_intr_status(hw,
PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
pcie_port_intr_info) +
csio_handle_intr_status(hw, PCIE_INT_CAUSE, pcie_intr_info);
csio_handle_intr_status(hw, PCIE_INT_CAUSE_A, pcie_intr_info);
if (fat)
csio_hw_fatal_err(hw);
}
@ -329,9 +329,9 @@ csio_t4_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
* the address is relative to BAR0.
*/
mem_reg = csio_rd_reg32(hw,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
mem_aperture = 1 << (WINDOW(mem_reg) + 10);
mem_base = GET_PCIEOFST(mem_reg) << 10;
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
mem_aperture = 1 << (WINDOW_V(mem_reg) + 10);
mem_base = PCIEOFST_G(mem_reg) << 10;
bar0 = csio_t4_read_pcie_cfg4(hw, PCI_BASE_ADDRESS_0);
bar0 &= PCI_BASE_ADDRESS_MEM_MASK;
@ -356,9 +356,9 @@ csio_t4_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
* before we attempt to use the new value.
*/
csio_wr_reg32(hw, pos,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
csio_rd_reg32(hw,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
while (offset < mem_aperture && len > 0) {
if (dir)

114
drivers/scsi/csiostor/csio_hw_t5.c
View File

@ -56,11 +56,11 @@ csio_t5_set_mem_win(struct csio_hw *hw, uint32_t win)
* back MA register to ensure that changes propagate before we attempt
* to use the new values.)
*/
csio_wr_reg32(hw, mem_win_base | BIR(0) |
WINDOW(ilog2(MEMWIN_APERTURE) - 10),
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
csio_wr_reg32(hw, mem_win_base | BIR_V(0) |
WINDOW_V(ilog2(MEMWIN_APERTURE) - 10),
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
csio_rd_reg32(hw,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
return 0;
}
@ -72,74 +72,74 @@ static void
csio_t5_pcie_intr_handler(struct csio_hw *hw)
{
static struct intr_info sysbus_intr_info[] = {
{ RNPP, "RXNP array parity error", -1, 1 },
{ RPCP, "RXPC array parity error", -1, 1 },
{ RCIP, "RXCIF array parity error", -1, 1 },
{ RCCP, "Rx completions control array parity error", -1, 1 },
{ RFTP, "RXFT array parity error", -1, 1 },
{ RNPP_F, "RXNP array parity error", -1, 1 },
{ RPCP_F, "RXPC array parity error", -1, 1 },
{ RCIP_F, "RXCIF array parity error", -1, 1 },
{ RCCP_F, "Rx completions control array parity error", -1, 1 },
{ RFTP_F, "RXFT array parity error", -1, 1 },
{ 0, NULL, 0, 0 }
};
static struct intr_info pcie_port_intr_info[] = {
{ TPCP, "TXPC array parity error", -1, 1 },
{ TNPP, "TXNP array parity error", -1, 1 },
{ TFTP, "TXFT array parity error", -1, 1 },
{ TCAP, "TXCA array parity error", -1, 1 },
{ TCIP, "TXCIF array parity error", -1, 1 },
{ RCAP, "RXCA array parity error", -1, 1 },
{ OTDD, "outbound request TLP discarded", -1, 1 },
{ RDPE, "Rx data parity error", -1, 1 },
{ TDUE, "Tx uncorrectable data error", -1, 1 },
{ TPCP_F, "TXPC array parity error", -1, 1 },
{ TNPP_F, "TXNP array parity error", -1, 1 },
{ TFTP_F, "TXFT array parity error", -1, 1 },
{ TCAP_F, "TXCA array parity error", -1, 1 },
{ TCIP_F, "TXCIF array parity error", -1, 1 },
{ RCAP_F, "RXCA array parity error", -1, 1 },
{ OTDD_F, "outbound request TLP discarded", -1, 1 },
{ RDPE_F, "Rx data parity error", -1, 1 },
{ TDUE_F, "Tx uncorrectable data error", -1, 1 },
{ 0, NULL, 0, 0 }
};
static struct intr_info pcie_intr_info[] = {
{ MSTGRPPERR, "Master Response Read Queue parity error",
{ MSTGRPPERR_F, "Master Response Read Queue parity error",
-1, 1 },
{ MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 },
{ MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 },
{ MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
{ MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
{ MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
{ MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
{ PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error",
{ MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
{ MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
{ MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
{ MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
{ MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
{ MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
{ PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
-1, 1 },
{ PIOREQGRPPERR, "PCI PIO request Group FIFO parity error",
{ PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
-1, 1 },
{ TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
{ MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 },
{ CREQPERR, "PCI CMD channel request parity error", -1, 1 },
{ CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
{ DREQWRPERR, "PCI DMA channel write request parity error",
{ TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
{ MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
{ CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
{ CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
{ DREQWRPERR_F, "PCI DMA channel write request parity error",
-1, 1 },
{ DREQPERR, "PCI DMA channel request parity error", -1, 1 },
{ DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
{ HREQWRPERR, "PCI HMA channel count parity error", -1, 1 },
{ HREQPERR, "PCI HMA channel request parity error", -1, 1 },
{ HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
{ CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
{ FIDPERR, "PCI FID parity error", -1, 1 },
{ VFIDPERR, "PCI INTx clear parity error", -1, 1 },
{ MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 },
{ PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
{ IPRXHDRGRPPERR, "PCI IP Rx header group parity error",
{ DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
{ DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
{ HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
{ HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
{ HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
{ CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
{ FIDPERR_F, "PCI FID parity error", -1, 1 },
{ VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
{ MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
{ PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
{ IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
-1, 1 },
{ IPRXDATAGRPPERR, "PCI IP Rx data group parity error",
{ IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
-1, 1 },
{ RPLPERR, "PCI IP replay buffer parity error", -1, 1 },
{ IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 },
{ TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 },
{ READRSPERR, "Outbound read error", -1, 0 },
{ RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
{ IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
{ TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
{ READRSPERR_F, "Outbound read error", -1, 0 },
{ 0, NULL, 0, 0 }
};
int fat;
fat = csio_handle_intr_status(hw,
PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
sysbus_intr_info) +
csio_handle_intr_status(hw,
PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
pcie_port_intr_info) +
csio_handle_intr_status(hw, PCIE_INT_CAUSE, pcie_intr_info);
csio_handle_intr_status(hw, PCIE_INT_CAUSE_A, pcie_intr_info);
if (fat)
csio_hw_fatal_err(hw);
}
@ -320,13 +320,13 @@ csio_t5_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
* the address is relative to BAR0.
*/
mem_reg = csio_rd_reg32(hw,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
mem_aperture = 1 << (WINDOW(mem_reg) + 10);
mem_base = GET_PCIEOFST(mem_reg) << 10;
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
mem_aperture = 1 << (WINDOW_V(mem_reg) + 10);
mem_base = PCIEOFST_G(mem_reg) << 10;
start = addr & ~(mem_aperture-1);
offset = addr - start;
win_pf = V_PFNUM(hw->pfn);
win_pf = PFNUM_V(hw->pfn);
csio_dbg(hw, "csio_t5_memory_rw: mem_reg: 0x%x, mem_aperture: 0x%x\n",
mem_reg, mem_aperture);
@ -344,9 +344,9 @@ csio_t5_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
* before we attempt to use the new value.
*/
csio_wr_reg32(hw, pos | win_pf,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
csio_rd_reg32(hw,
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
while (offset < mem_aperture && len > 0) {
if (dir)

2
drivers/scsi/csiostor/csio_isr.c
View File

@ -317,7 +317,7 @@ csio_fcoe_isr(int irq, void *dev_id)
/* Disable the interrupt for this PCI function. */
if (hw->intr_mode == CSIO_IM_INTX)
csio_wr_reg32(hw, 0, MYPF_REG(PCIE_PF_CLI));
csio_wr_reg32(hw, 0, MYPF_REG(PCIE_PF_CLI_A));
/*
* The read in the following function will flush the

36
drivers/scsi/csiostor/csio_wr.c
View File

@ -1412,22 +1412,22 @@ csio_wr_get_sge(struct csio_hw *hw)
for (i = 0; i < CSIO_SGE_FL_SIZE_REGS; i++)
csio_get_flbuf_size(hw, sge, i);
timer_value_0_and_1 = csio_rd_reg32(hw, SGE_TIMER_VALUE_0_AND_1);
timer_value_2_and_3 = csio_rd_reg32(hw, SGE_TIMER_VALUE_2_AND_3);
timer_value_4_and_5 = csio_rd_reg32(hw, SGE_TIMER_VALUE_4_AND_5);
timer_value_0_and_1 = csio_rd_reg32(hw, SGE_TIMER_VALUE_0_AND_1_A);
timer_value_2_and_3 = csio_rd_reg32(hw, SGE_TIMER_VALUE_2_AND_3_A);
timer_value_4_and_5 = csio_rd_reg32(hw, SGE_TIMER_VALUE_4_AND_5_A);
sge->timer_val[0] = (uint16_t)csio_core_ticks_to_us(hw,
TIMERVALUE0_GET(timer_value_0_and_1));
TIMERVALUE0_G(timer_value_0_and_1));
sge->timer_val[1] = (uint16_t)csio_core_ticks_to_us(hw,
TIMERVALUE1_GET(timer_value_0_and_1));
TIMERVALUE1_G(timer_value_0_and_1));
sge->timer_val[2] = (uint16_t)csio_core_ticks_to_us(hw,
TIMERVALUE2_GET(timer_value_2_and_3));
TIMERVALUE2_G(timer_value_2_and_3));
sge->timer_val[3] = (uint16_t)csio_core_ticks_to_us(hw,
TIMERVALUE3_GET(timer_value_2_and_3));
TIMERVALUE3_G(timer_value_2_and_3));
sge->timer_val[4] = (uint16_t)csio_core_ticks_to_us(hw,
TIMERVALUE4_GET(timer_value_4_and_5));
TIMERVALUE4_G(timer_value_4_and_5));
sge->timer_val[5] = (uint16_t)csio_core_ticks_to_us(hw,
TIMERVALUE5_GET(timer_value_4_and_5));
TIMERVALUE5_G(timer_value_4_and_5));
ingress_rx_threshold = csio_rd_reg32(hw, SGE_INGRESS_RX_THRESHOLD_A);
sge->counter_val[0] = THRESHOLD_0_G(ingress_rx_threshold);
@ -1513,19 +1513,19 @@ csio_wr_set_sge(struct csio_hw *hw)
SGE_INGRESS_RX_THRESHOLD_A);
csio_wr_reg32(hw,
TIMERVALUE0(csio_us_to_core_ticks(hw, sge->timer_val[0])) |
TIMERVALUE1(csio_us_to_core_ticks(hw, sge->timer_val[1])),
SGE_TIMER_VALUE_0_AND_1);
TIMERVALUE0_V(csio_us_to_core_ticks(hw, sge->timer_val[0])) |
TIMERVALUE1_V(csio_us_to_core_ticks(hw, sge->timer_val[1])),
SGE_TIMER_VALUE_0_AND_1_A);
csio_wr_reg32(hw,
TIMERVALUE2(csio_us_to_core_ticks(hw, sge->timer_val[2])) |
TIMERVALUE3(csio_us_to_core_ticks(hw, sge->timer_val[3])),
SGE_TIMER_VALUE_2_AND_3);
TIMERVALUE2_V(csio_us_to_core_ticks(hw, sge->timer_val[2])) |
TIMERVALUE3_V(csio_us_to_core_ticks(hw, sge->timer_val[3])),
SGE_TIMER_VALUE_2_AND_3_A);
csio_wr_reg32(hw,
TIMERVALUE4(csio_us_to_core_ticks(hw, sge->timer_val[4])) |
TIMERVALUE5(csio_us_to_core_ticks(hw, sge->timer_val[5])),
SGE_TIMER_VALUE_4_AND_5);
TIMERVALUE4_V(csio_us_to_core_ticks(hw, sge->timer_val[4])) |
TIMERVALUE5_V(csio_us_to_core_ticks(hw, sge->timer_val[5])),
SGE_TIMER_VALUE_4_AND_5_A);
csio_init_intr_coalesce_parms(hw);
}