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drm: Add the basic check for the detailed timing in EDID
Sometimes we will get the incorrect display modeline when parsing the detailed timing in EDID. For example: >hsync/vsync width is zero >sync is beyond the blank. So add the basic check for the detailed timing in EDID to avoid the incorrect display modeline. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -626,6 +626,12 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
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return NULL;
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}
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/* it is incorrect if hsync/vsync width is zero */
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if (!hsync_pulse_width || !vsync_pulse_width) {
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DRM_DEBUG_KMS("Incorrect Detailed timing. "
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"Wrong Hsync/Vsync pulse width\n");
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return NULL;
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}
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mode = drm_mode_create(dev);
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if (!mode)
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return NULL;
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@ -647,6 +653,15 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
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mode->vsync_end = mode->vsync_start + vsync_pulse_width;
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mode->vtotal = mode->vdisplay + vblank;
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/* perform the basic check for the detailed timing */
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if (mode->hsync_end > mode->htotal ||
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mode->vsync_end > mode->vtotal) {
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drm_mode_destroy(dev, mode);
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DRM_DEBUG_KMS("Incorrect detailed timing. "
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"Sync is beyond the blank.\n");
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return NULL;
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}
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drm_mode_set_name(mode);
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if (pt->misc & DRM_EDID_PT_INTERLACED)
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