mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-29 07:34:06 +08:00
dt-bindings: reset: uniphier: add USB3 core reset support
Add DT bindings for reset control of USB3 core implemented in UniPhier SoCs. The reset control belongs to USB3 glue layer. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
This commit is contained in:
parent
9ad39ab280
commit
ef8b023b23
@ -118,3 +118,59 @@ Example:
|
||||
|
||||
other nodes ...
|
||||
};
|
||||
|
||||
|
||||
USB3 core reset
|
||||
---------------
|
||||
|
||||
USB3 core reset belongs to USB3 glue layer. Before using the core reset,
|
||||
it is necessary to control the clocks and resets to enable this layer.
|
||||
These clocks and resets should be described in each property.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be
|
||||
"socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC
|
||||
"socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC
|
||||
"socionext,uniphier-ld20-usb3-reset" - for LD20 SoC
|
||||
"socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC
|
||||
- #reset-cells: Should be 1.
|
||||
- reg: Specifies offset and length of the register set for the device.
|
||||
- clocks: A list of phandles to the clock gate for USB3 glue layer.
|
||||
According to the clock-names, appropriate clocks are required.
|
||||
- clock-names: Should contain
|
||||
"gio", "link" - for Pro4 SoC
|
||||
"link" - for others
|
||||
- resets: A list of phandles to the reset control for USB3 glue layer.
|
||||
According to the reset-names, appropriate resets are required.
|
||||
- reset-names: Should contain
|
||||
"gio", "link" - for Pro4 SoC
|
||||
"link" - for others
|
||||
|
||||
Example:
|
||||
|
||||
usb-glue@65b00000 {
|
||||
compatible = "socionext,uniphier-ld20-dwc3-glue",
|
||||
"simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x65b00000 0x400>;
|
||||
|
||||
usb_rst: reset@0 {
|
||||
compatible = "socionext,uniphier-ld20-usb3-reset";
|
||||
reg = <0x0 0x4>;
|
||||
#reset-cells = <1>;
|
||||
clock-names = "link";
|
||||
clocks = <&sys_clk 14>;
|
||||
reset-names = "link";
|
||||
resets = <&sys_rst 14>;
|
||||
};
|
||||
|
||||
regulator {
|
||||
...
|
||||
};
|
||||
|
||||
phy {
|
||||
...
|
||||
};
|
||||
...
|
||||
};
|
||||
|
Loading…
Reference in New Issue
Block a user