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drm/amd/powerplay: enable uclk dpm default on navi10
enable uclk (mclk) dpm by default on navi10 Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -314,6 +314,9 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
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| FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
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| FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
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| FEATURE_MASK(FEATURE_DPM_LINK_BIT)
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| FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
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| FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
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| FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT)
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| FEATURE_MASK(FEATURE_GFX_ULV_BIT)
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| FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
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| FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
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@ -332,11 +335,6 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
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| FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
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| FEATURE_MASK(FEATURE_ACDC_BIT);
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if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
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*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
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| FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
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| FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
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if (adev->pm.pp_feature & PP_GFXOFF_MASK)
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*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
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| FEATURE_MASK(FEATURE_GFXOFF_BIT);
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@ -350,7 +348,9 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
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if ((adev->asic_type == CHIP_NAVI10) &&
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(adev->rev_id == 0)) {
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*(uint64_t *)feature_mask &=
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~FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
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~(FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
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| FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
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| FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT));
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*(uint64_t *)feature_mask &=
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~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
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}
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