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ASoC: mediatek: add power-domains for mt2701-afe-pcm.txt

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This add power-domains for mt2701-afe-pcm

Signed-off-by: Garlic Tseng <garlic.tseng@mediatek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Garlic Tseng 2017-02-16 13:27:16 +08:00 committed by Mark Brown
parent cc3e1ce2c7
commit ee9dc31962
1 changed files with 2 additions and 0 deletions
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Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
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@ -4,6 +4,7 @@ Required properties:
- compatible = "mediatek,mt2701-audio"; - compatible = "mediatek,mt2701-audio";
- reg: register location and size - reg: register location and size
- interrupts: Should contain AFE interrupt - interrupts: Should contain AFE interrupt
- power-domains: should define the power domain
- clock-names: should have these clock names: - clock-names: should have these clock names:
"infra_sys_audio_clk", "infra_sys_audio_clk",
"top_audio_mux1_sel", "top_audio_mux1_sel",
@ -58,6 +59,7 @@ Example:
<0 0x112A0000 0 0x20000>; <0 0x112A0000 0 0x20000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
clocks = <&infracfg CLK_INFRA_AUDIO>, clocks = <&infracfg CLK_INFRA_AUDIO>,
<&topckgen CLK_TOP_AUD_MUX1_SEL>, <&topckgen CLK_TOP_AUD_MUX1_SEL>,
<&topckgen CLK_TOP_AUD_MUX2_SEL>, <&topckgen CLK_TOP_AUD_MUX2_SEL>,