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ath5k: Use new srevs to properly attach radio chips
* Use new SREV values and PHY srevs to identify radio type durring attach Changes-Licensed-under: ISC Signed-Off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Nick Kossifidis
John W. Linville
parent
1d280ddcfd
commit
ee81c5544b
@ -137,7 +137,7 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
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ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
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/*
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* Set the mac revision based on the pci id
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* Set the mac version based on the pci id
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*/
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ah->ah_version = mac_version;
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@ -160,12 +160,103 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
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0xffffffff;
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ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
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CHANNEL_5GHZ);
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ah->ah_phy = AR5K_PHY(0);
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if (ah->ah_version == AR5K_AR5210)
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ah->ah_radio_2ghz_revision = 0;
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else
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/* Try to identify radio chip based on it's srev */
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switch (ah->ah_radio_5ghz_revision & 0xf0) {
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case AR5K_SREV_RAD_5111:
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ah->ah_radio = AR5K_RF5111;
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ah->ah_single_chip = false;
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ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
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CHANNEL_2GHZ);
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CHANNEL_2GHZ);
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5111;
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break;
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case AR5K_SREV_RAD_5112:
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case AR5K_SREV_RAD_2112:
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ah->ah_radio = AR5K_RF5112;
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ah->ah_single_chip = false;
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ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
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CHANNEL_2GHZ);
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
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break;
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case AR5K_SREV_RAD_2413:
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ah->ah_radio = AR5K_RF2413;
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ah->ah_single_chip = true;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
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break;
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case AR5K_SREV_RAD_5413:
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ah->ah_radio = AR5K_RF5413;
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ah->ah_single_chip = true;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
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break;
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case AR5K_SREV_RAD_2316:
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ah->ah_radio = AR5K_RF2316;
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ah->ah_single_chip = true;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2316;
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break;
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case AR5K_SREV_RAD_2317:
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ah->ah_radio = AR5K_RF2317;
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ah->ah_single_chip = true;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2317;
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break;
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case AR5K_SREV_RAD_5424:
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if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
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ah->ah_mac_version == AR5K_SREV_AR2417){
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ah->ah_radio = AR5K_RF2425;
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ah->ah_single_chip = true;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425;
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} else {
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ah->ah_radio = AR5K_RF5413;
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ah->ah_single_chip = true;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
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}
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break;
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default:
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/* Identify radio based on mac/phy srev */
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if (ah->ah_version == AR5K_AR5210) {
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ah->ah_radio = AR5K_RF5110;
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ah->ah_single_chip = false;
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} else if (ah->ah_version == AR5K_AR5211) {
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ah->ah_radio = AR5K_RF5111;
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ah->ah_single_chip = false;
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ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
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CHANNEL_2GHZ);
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} else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
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ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
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ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
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ah->ah_radio = AR5K_RF2425;
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ah->ah_single_chip = true;
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ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425;
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} else if (srev == AR5K_SREV_AR5213A &&
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ah->ah_phy_revision == AR5K_SREV_PHY_2112B) {
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ah->ah_radio = AR5K_RF5112;
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ah->ah_single_chip = false;
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ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2112B;
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} else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
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ah->ah_radio = AR5K_RF2316;
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ah->ah_single_chip = true;
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ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2316;
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} else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
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ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
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ah->ah_radio = AR5K_RF5413;
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ah->ah_single_chip = true;
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ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
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} else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
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ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
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ah->ah_radio = AR5K_RF2413;
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ah->ah_single_chip = true;
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ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
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} else {
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ATH5K_ERR(sc, "Couldn't identify radio revision.\n");
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ret = -ENODEV;
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goto err_free;
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}
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}
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/* Return on unsuported chips (unsupported eeprom etc) */
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if ((srev >= AR5K_SREV_AR5416) &&
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@ -173,74 +264,28 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
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ATH5K_ERR(sc, "Device not yet supported.\n");
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ret = -ENODEV;
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goto err_free;
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} else if (srev == AR5K_SREV_AR2425) {
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ATH5K_WARN(sc, "Support for RF2425 is under development.\n");
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}
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/* Identify single chip solutions */
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if (((srev <= AR5K_SREV_AR5414) &&
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(srev >= AR5K_SREV_AR2413)) ||
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(srev == AR5K_SREV_AR2425)) {
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ah->ah_single_chip = true;
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} else {
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ah->ah_single_chip = false;
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}
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/* Single chip radio */
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if (ah->ah_radio_2ghz_revision == ah->ah_radio_5ghz_revision)
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ah->ah_radio_2ghz_revision = 0;
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/* Identify the radio chip*/
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if (ah->ah_version == AR5K_AR5210) {
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ah->ah_radio = AR5K_RF5110;
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/*
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* Register returns 0x0/0x04 for radio revision
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* so ath5k_hw_radio_revision doesn't parse the value
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* correctly. For now we are based on mac's srev to
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* identify RF2425 radio.
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*/
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} else if (srev == AR5K_SREV_AR2425) {
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ah->ah_radio = AR5K_RF2425;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2425;
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} else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) {
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ah->ah_radio = AR5K_RF5111;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5111;
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} else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_2413) {
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ah->ah_radio = AR5K_RF5112;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
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} else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5413) {
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ah->ah_radio = AR5K_RF2413;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
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} else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_2316) {
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ah->ah_radio = AR5K_RF5413;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
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} else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5133) {
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/* AR5424 */
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if (srev >= AR5K_SREV_AR5424) {
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ah->ah_radio = AR5K_RF5413;
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5413;
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/* AR2424 */
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} else {
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ah->ah_radio = AR5K_RF2413; /* For testing */
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ah->ah_phy_spending = AR5K_PHY_SPENDING_RF2413;
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}
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}
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ah->ah_phy = AR5K_PHY(0);
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/*
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* Write PCI-E power save settings
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*/
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if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
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ath5k_hw_reg_write(ah, 0x9248fc00, 0x4080);
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ath5k_hw_reg_write(ah, 0x24924924, 0x4080);
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ath5k_hw_reg_write(ah, 0x28000039, 0x4080);
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ath5k_hw_reg_write(ah, 0x53160824, 0x4080);
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ath5k_hw_reg_write(ah, 0xe5980579, 0x4080);
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ath5k_hw_reg_write(ah, 0x001defff, 0x4080);
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ath5k_hw_reg_write(ah, 0x1aaabe40, 0x4080);
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ath5k_hw_reg_write(ah, 0xbe105554, 0x4080);
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ath5k_hw_reg_write(ah, 0x000e3007, 0x4080);
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ath5k_hw_reg_write(ah, 0x00000000, 0x4084);
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ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
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ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
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/* Shut off RX when elecidle is asserted */
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ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
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ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
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/* TODO: EEPROM work */
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ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
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/* Shut off PLL and CLKREQ active in L1 */
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ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
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/* Preserce other settings */
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ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
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ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
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ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
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/* Reset SERDES to load new settings */
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ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
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mdelay(1);
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}
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/*
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@ -250,14 +295,13 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
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if (ret)
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goto err_free;
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/* Write AR5K_PCICFG_UNK on 2112B and later chips */
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if (ah->ah_radio_5ghz_revision > AR5K_SREV_RAD_2112B ||
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srev > AR5K_SREV_AR2413) {
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/* Enable pci core retry fix on Hainan (5213A) and later chips */
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if (srev >= AR5K_SREV_AR5213A)
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ath5k_hw_reg_write(ah, AR5K_PCICFG_RETRY_FIX, AR5K_PCICFG);
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}
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/*
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* Get card capabilities, values, ...
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* Get card capabilities, calibration values etc
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* TODO: EEPROM work
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*/
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ret = ath5k_eeprom_init(ah);
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if (ret) {
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@ -273,7 +317,7 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
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goto err_free;
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}
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/* Get MAC address */
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/* Set MAC address */
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ret = ath5k_eeprom_read_mac(ah, mac);
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if (ret) {
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ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
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