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clk: samsung: exynos7: add clocks for SPI block
Add clock support for 5 SPI channels. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Padmavathi Venna
Sylwester Nawrocki
parent
9cc2a0c95f
commit
ee74b56ab2
@ -77,6 +77,11 @@ Input clocks for peric1 clock controller:
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- sclk_uart1
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- sclk_uart2
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- sclk_uart3
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- sclk_spi0
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- sclk_spi1
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- sclk_spi2
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- sclk_spi3
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- sclk_spi4
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Input clocks for peris clock controller:
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- fin_pll
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@ -177,9 +177,15 @@ CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
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#define MUX_SEL_TOP00 0x0200
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#define MUX_SEL_TOP01 0x0204
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#define MUX_SEL_TOP03 0x020C
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#define MUX_SEL_TOP0_PERIC1 0x0234
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#define MUX_SEL_TOP0_PERIC2 0x0238
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#define MUX_SEL_TOP0_PERIC3 0x023C
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#define DIV_TOP03 0x060C
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#define DIV_TOP0_PERIC1 0x0634
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#define DIV_TOP0_PERIC2 0x0638
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#define DIV_TOP0_PERIC3 0x063C
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#define ENABLE_SCLK_TOP0_PERIC1 0x0A34
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#define ENABLE_SCLK_TOP0_PERIC2 0x0A38
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#define ENABLE_SCLK_TOP0_PERIC3 0x0A3C
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/* List of parent clocks for Muxes in CMU_TOP0 */
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@ -205,9 +211,15 @@ static unsigned long top0_clk_regs[] __initdata = {
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MUX_SEL_TOP00,
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MUX_SEL_TOP01,
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MUX_SEL_TOP03,
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MUX_SEL_TOP0_PERIC1,
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MUX_SEL_TOP0_PERIC2,
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MUX_SEL_TOP0_PERIC3,
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DIV_TOP03,
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DIV_TOP0_PERIC1,
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DIV_TOP0_PERIC2,
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DIV_TOP0_PERIC3,
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ENABLE_SCLK_TOP0_PERIC1,
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ENABLE_SCLK_TOP0_PERIC2,
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ENABLE_SCLK_TOP0_PERIC3,
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};
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@ -229,10 +241,16 @@ static struct samsung_mux_clock top0_mux_clks[] __initdata = {
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MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
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MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
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MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
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MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
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MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
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MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
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MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
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MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
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MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
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MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
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MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
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};
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static struct samsung_div_clock top0_div_clks[] __initdata = {
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@ -241,13 +259,29 @@ static struct samsung_div_clock top0_div_clks[] __initdata = {
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DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
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DIV_TOP03, 20, 6),
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DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12),
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DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12),
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DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12),
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DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12),
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DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
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DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
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DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
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DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
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DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12),
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};
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static struct samsung_gate_clock top0_gate_clks[] __initdata = {
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GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1",
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ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
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ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3",
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ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2",
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ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
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ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
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GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
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@ -256,6 +290,8 @@ static struct samsung_gate_clock top0_gate_clks[] __initdata = {
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ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
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GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
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ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
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GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4",
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ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
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};
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static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
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@ -531,6 +567,7 @@ static void __init exynos7_clk_peric0_init(struct device_node *np)
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/* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
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#define MUX_SEL_PERIC10 0x0200
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#define MUX_SEL_PERIC11 0x0204
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#define MUX_SEL_PERIC12 0x0208
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#define ENABLE_PCLK_PERIC1 0x0900
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#define ENABLE_SCLK_PERIC10 0x0A00
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@ -542,10 +579,16 @@ PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" };
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PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" };
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PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" };
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PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" };
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PNAME(mout_sclk_spi0_p) = { "fin_pll", "sclk_spi0" };
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PNAME(mout_sclk_spi1_p) = { "fin_pll", "sclk_spi1" };
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PNAME(mout_sclk_spi2_p) = { "fin_pll", "sclk_spi2" };
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PNAME(mout_sclk_spi3_p) = { "fin_pll", "sclk_spi3" };
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PNAME(mout_sclk_spi4_p) = { "fin_pll", "sclk_spi4" };
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static unsigned long peric1_clk_regs[] __initdata = {
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MUX_SEL_PERIC10,
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MUX_SEL_PERIC11,
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MUX_SEL_PERIC12,
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ENABLE_PCLK_PERIC1,
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ENABLE_SCLK_PERIC10,
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};
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@ -554,6 +597,16 @@ static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
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MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p,
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MUX_SEL_PERIC10, 0, 1),
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MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_p,
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MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
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MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_p,
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MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
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MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_p,
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MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
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MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_p,
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MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
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MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_p,
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MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
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MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p,
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MUX_SEL_PERIC11, 20, 1),
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MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p,
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@ -579,6 +632,16 @@ static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
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ENABLE_PCLK_PERIC1, 10, 0, 0),
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GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
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ENABLE_PCLK_PERIC1, 11, 0, 0),
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GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user",
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ENABLE_PCLK_PERIC1, 12, 0, 0),
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GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user",
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ENABLE_PCLK_PERIC1, 13, 0, 0),
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GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user",
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ENABLE_PCLK_PERIC1, 14, 0, 0),
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GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user",
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ENABLE_PCLK_PERIC1, 15, 0, 0),
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GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user",
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ENABLE_PCLK_PERIC1, 16, 0, 0),
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GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
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ENABLE_SCLK_PERIC10, 9, 0, 0),
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@ -586,6 +649,16 @@ static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
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ENABLE_SCLK_PERIC10, 10, 0, 0),
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GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
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ENABLE_SCLK_PERIC10, 11, 0, 0),
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GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user",
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ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0),
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GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user",
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ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0),
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GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user",
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ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0),
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GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user",
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ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0),
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GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user",
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ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0),
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};
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static struct samsung_cmu_info peric1_cmu_info __initdata = {
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@ -28,7 +28,12 @@
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#define CLK_SCLK_UART1 4
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#define CLK_SCLK_UART2 5
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#define CLK_SCLK_UART3 6
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#define TOP0_NR_CLK 7
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#define CLK_SCLK_SPI0 7
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#define CLK_SCLK_SPI1 8
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#define CLK_SCLK_SPI2 9
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#define CLK_SCLK_SPI3 10
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#define CLK_SCLK_SPI4 11
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#define TOP0_NR_CLK 12
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/* TOP1 */
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#define DOUT_ACLK_FSYS1_200 1
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@ -72,7 +77,17 @@
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#define PCLK_HSI2C6 9
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#define PCLK_HSI2C7 10
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#define PCLK_HSI2C8 11
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#define PERIC1_NR_CLK 12
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#define PCLK_SPI0 12
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#define PCLK_SPI1 13
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#define PCLK_SPI2 14
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#define PCLK_SPI3 15
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#define PCLK_SPI4 16
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#define SCLK_SPI0 17
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#define SCLK_SPI1 18
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#define SCLK_SPI2 19
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#define SCLK_SPI3 20
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#define SCLK_SPI4 21
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#define PERIC1_NR_CLK 22
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/* PERIS */
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#define PCLK_CHIPID 1
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