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powerpc/watchpoint: Move DAWR detection logic outside of hw_breakpoint.c
Power10 hw has multiple DAWRs but hw doesn't tell which DAWR caused the exception. So we have a sw logic to detect that in hw_breakpoint.c. But hw_breakpoint.c gets compiled only with CONFIG_HAVE_HW_BREAKPOINT=Y. Move DAWR detection logic outside of hw_breakpoint.c so that it can be reused when CONFIG_HAVE_HW_BREAKPOINT is not set. Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200902042945.129369-5-ravi.bangoria@linux.ibm.com
This commit is contained in:
Ravi Bangoria
Michael Ellerman
parent
9b6b7c680c
commit
edc8dd99b2
@ -10,6 +10,7 @@
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#define _PPC_BOOK3S_64_HW_BREAKPOINT_H
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#include <asm/cpu_has_feature.h>
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#include <asm/inst.h>
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#ifdef __KERNEL__
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struct arch_hw_breakpoint {
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@ -52,6 +53,13 @@ static inline int nr_wp_slots(void)
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return cpu_has_feature(CPU_FTR_DAWR1) ? 2 : 1;
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}
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bool wp_check_constraints(struct pt_regs *regs, struct ppc_inst instr,
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unsigned long ea, int type, int size,
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struct arch_hw_breakpoint *info);
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void wp_get_instr_detail(struct pt_regs *regs, struct ppc_inst *instr,
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int *type, int *size, unsigned long *ea);
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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#include <linux/kdebug.h>
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#include <asm/reg.h>
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@ -45,7 +45,8 @@ obj-y := cputable.o syscalls.o \
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signal.o sysfs.o cacheinfo.o time.o \
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prom.o traps.o setup-common.o \
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udbg.o misc.o io.o misc_$(BITS).o \
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of_platform.o prom_parse.o firmware.o
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of_platform.o prom_parse.o firmware.o \
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hw_breakpoint_constraints.o
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obj-y += ptrace/
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obj-$(CONFIG_PPC64) += setup_64.o \
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paca.o nvram_64.o note.o syscall_64.o
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@ -494,161 +494,6 @@ reset:
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}
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}
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static bool dar_in_user_range(unsigned long dar, struct arch_hw_breakpoint *info)
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{
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return ((info->address <= dar) && (dar - info->address < info->len));
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}
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static bool ea_user_range_overlaps(unsigned long ea, int size,
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struct arch_hw_breakpoint *info)
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{
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return ((ea < info->address + info->len) &&
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(ea + size > info->address));
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}
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static bool dar_in_hw_range(unsigned long dar, struct arch_hw_breakpoint *info)
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{
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unsigned long hw_start_addr, hw_end_addr;
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hw_start_addr = ALIGN_DOWN(info->address, HW_BREAKPOINT_SIZE);
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hw_end_addr = ALIGN(info->address + info->len, HW_BREAKPOINT_SIZE);
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return ((hw_start_addr <= dar) && (hw_end_addr > dar));
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}
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static bool ea_hw_range_overlaps(unsigned long ea, int size,
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struct arch_hw_breakpoint *info)
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{
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unsigned long hw_start_addr, hw_end_addr;
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unsigned long align_size = HW_BREAKPOINT_SIZE;
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/*
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* On p10 predecessors, quadword is handle differently then
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* other instructions.
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*/
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if (!cpu_has_feature(CPU_FTR_ARCH_31) && size == 16)
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align_size = HW_BREAKPOINT_SIZE_QUADWORD;
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hw_start_addr = ALIGN_DOWN(info->address, align_size);
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hw_end_addr = ALIGN(info->address + info->len, align_size);
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return ((ea < hw_end_addr) && (ea + size > hw_start_addr));
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}
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/*
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* If hw has multiple DAWR registers, we also need to check all
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* dawrx constraint bits to confirm this is _really_ a valid event.
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* If type is UNKNOWN, but privilege level matches, consider it as
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* a positive match.
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*/
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static bool check_dawrx_constraints(struct pt_regs *regs, int type,
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struct arch_hw_breakpoint *info)
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{
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if (OP_IS_LOAD(type) && !(info->type & HW_BRK_TYPE_READ))
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return false;
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/*
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* The Cache Management instructions other than dcbz never
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* cause a match. i.e. if type is CACHEOP, the instruction
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* is dcbz, and dcbz is treated as Store.
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*/
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if ((OP_IS_STORE(type) || type == CACHEOP) && !(info->type & HW_BRK_TYPE_WRITE))
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return false;
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if (is_kernel_addr(regs->nip) && !(info->type & HW_BRK_TYPE_KERNEL))
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return false;
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if (user_mode(regs) && !(info->type & HW_BRK_TYPE_USER))
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return false;
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return true;
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}
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/*
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* Return true if the event is valid wrt dawr configuration,
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* including extraneous exception. Otherwise return false.
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*/
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static bool check_constraints(struct pt_regs *regs, struct ppc_inst instr,
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unsigned long ea, int type, int size,
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struct arch_hw_breakpoint *info)
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{
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bool in_user_range = dar_in_user_range(regs->dar, info);
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bool dawrx_constraints;
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/*
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* 8xx supports only one breakpoint and thus we can
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* unconditionally return true.
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*/
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if (IS_ENABLED(CONFIG_PPC_8xx)) {
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if (!in_user_range)
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info->type |= HW_BRK_TYPE_EXTRANEOUS_IRQ;
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return true;
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}
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if (unlikely(ppc_inst_equal(instr, ppc_inst(0)))) {
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if (cpu_has_feature(CPU_FTR_ARCH_31) &&
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!dar_in_hw_range(regs->dar, info))
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return false;
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return true;
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}
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dawrx_constraints = check_dawrx_constraints(regs, type, info);
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if (type == UNKNOWN) {
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if (cpu_has_feature(CPU_FTR_ARCH_31) &&
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!dar_in_hw_range(regs->dar, info))
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return false;
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return dawrx_constraints;
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}
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if (ea_user_range_overlaps(ea, size, info))
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return dawrx_constraints;
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if (ea_hw_range_overlaps(ea, size, info)) {
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if (dawrx_constraints) {
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info->type |= HW_BRK_TYPE_EXTRANEOUS_IRQ;
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return true;
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}
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}
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return false;
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}
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static int cache_op_size(void)
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{
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#ifdef __powerpc64__
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return ppc64_caches.l1d.block_size;
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#else
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return L1_CACHE_BYTES;
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#endif
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}
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static void get_instr_detail(struct pt_regs *regs, struct ppc_inst *instr,
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int *type, int *size, unsigned long *ea)
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{
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struct instruction_op op;
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if (__get_user_instr_inatomic(*instr, (void __user *)regs->nip))
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return;
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analyse_instr(&op, regs, *instr);
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*type = GETTYPE(op.type);
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*ea = op.ea;
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#ifdef __powerpc64__
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if (!(regs->msr & MSR_64BIT))
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*ea &= 0xffffffffUL;
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#endif
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*size = GETSIZE(op.type);
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if (*type == CACHEOP) {
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*size = cache_op_size();
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*ea &= ~(*size - 1);
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} else if (*type == LOAD_VMX || *type == STORE_VMX) {
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*ea &= ~(*size - 1);
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}
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}
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static bool is_larx_stcx_instr(int type)
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{
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return type == LARX || type == STCX;
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@ -732,7 +577,7 @@ int hw_breakpoint_handler(struct die_args *args)
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rcu_read_lock();
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if (!IS_ENABLED(CONFIG_PPC_8xx))
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get_instr_detail(regs, &instr, &type, &size, &ea);
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wp_get_instr_detail(regs, &instr, &type, &size, &ea);
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for (i = 0; i < nr_wp_slots(); i++) {
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bp[i] = __this_cpu_read(bp_per_reg[i]);
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@ -742,7 +587,7 @@ int hw_breakpoint_handler(struct die_args *args)
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info[i] = counter_arch_bp(bp[i]);
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info[i]->type &= ~HW_BRK_TYPE_EXTRANEOUS_IRQ;
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if (check_constraints(regs, instr, ea, type, size, info[i])) {
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if (wp_check_constraints(regs, instr, ea, type, size, info[i])) {
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if (!IS_ENABLED(CONFIG_PPC_8xx) &&
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ppc_inst_equal(instr, ppc_inst(0))) {
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handler_error(bp[i], info[i]);
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162
arch/powerpc/kernel/hw_breakpoint_constraints.c
Normal file
162
arch/powerpc/kernel/hw_breakpoint_constraints.c
Normal file
@ -0,0 +1,162 @@
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// SPDX-License-Identifier: GPL-2.0+
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#include <linux/kernel.h>
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#include <linux/uaccess.h>
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#include <linux/sched.h>
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#include <asm/hw_breakpoint.h>
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#include <asm/sstep.h>
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#include <asm/cache.h>
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static bool dar_in_user_range(unsigned long dar, struct arch_hw_breakpoint *info)
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{
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return ((info->address <= dar) && (dar - info->address < info->len));
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}
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static bool ea_user_range_overlaps(unsigned long ea, int size,
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struct arch_hw_breakpoint *info)
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{
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return ((ea < info->address + info->len) &&
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(ea + size > info->address));
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}
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static bool dar_in_hw_range(unsigned long dar, struct arch_hw_breakpoint *info)
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{
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unsigned long hw_start_addr, hw_end_addr;
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hw_start_addr = ALIGN_DOWN(info->address, HW_BREAKPOINT_SIZE);
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hw_end_addr = ALIGN(info->address + info->len, HW_BREAKPOINT_SIZE);
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return ((hw_start_addr <= dar) && (hw_end_addr > dar));
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}
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static bool ea_hw_range_overlaps(unsigned long ea, int size,
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struct arch_hw_breakpoint *info)
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{
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unsigned long hw_start_addr, hw_end_addr;
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unsigned long align_size = HW_BREAKPOINT_SIZE;
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/*
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* On p10 predecessors, quadword is handle differently then
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* other instructions.
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*/
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if (!cpu_has_feature(CPU_FTR_ARCH_31) && size == 16)
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align_size = HW_BREAKPOINT_SIZE_QUADWORD;
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hw_start_addr = ALIGN_DOWN(info->address, align_size);
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hw_end_addr = ALIGN(info->address + info->len, align_size);
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return ((ea < hw_end_addr) && (ea + size > hw_start_addr));
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}
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/*
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* If hw has multiple DAWR registers, we also need to check all
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* dawrx constraint bits to confirm this is _really_ a valid event.
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* If type is UNKNOWN, but privilege level matches, consider it as
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* a positive match.
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*/
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static bool check_dawrx_constraints(struct pt_regs *regs, int type,
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struct arch_hw_breakpoint *info)
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{
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if (OP_IS_LOAD(type) && !(info->type & HW_BRK_TYPE_READ))
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return false;
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/*
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* The Cache Management instructions other than dcbz never
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* cause a match. i.e. if type is CACHEOP, the instruction
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* is dcbz, and dcbz is treated as Store.
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*/
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if ((OP_IS_STORE(type) || type == CACHEOP) && !(info->type & HW_BRK_TYPE_WRITE))
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return false;
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if (is_kernel_addr(regs->nip) && !(info->type & HW_BRK_TYPE_KERNEL))
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return false;
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if (user_mode(regs) && !(info->type & HW_BRK_TYPE_USER))
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return false;
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return true;
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}
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/*
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* Return true if the event is valid wrt dawr configuration,
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* including extraneous exception. Otherwise return false.
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*/
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bool wp_check_constraints(struct pt_regs *regs, struct ppc_inst instr,
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unsigned long ea, int type, int size,
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struct arch_hw_breakpoint *info)
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{
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bool in_user_range = dar_in_user_range(regs->dar, info);
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bool dawrx_constraints;
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/*
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* 8xx supports only one breakpoint and thus we can
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* unconditionally return true.
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*/
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if (IS_ENABLED(CONFIG_PPC_8xx)) {
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if (!in_user_range)
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info->type |= HW_BRK_TYPE_EXTRANEOUS_IRQ;
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return true;
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}
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if (unlikely(ppc_inst_equal(instr, ppc_inst(0)))) {
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if (cpu_has_feature(CPU_FTR_ARCH_31) &&
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!dar_in_hw_range(regs->dar, info))
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return false;
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return true;
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}
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dawrx_constraints = check_dawrx_constraints(regs, type, info);
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if (type == UNKNOWN) {
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if (cpu_has_feature(CPU_FTR_ARCH_31) &&
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!dar_in_hw_range(regs->dar, info))
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return false;
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return dawrx_constraints;
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}
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if (ea_user_range_overlaps(ea, size, info))
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return dawrx_constraints;
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if (ea_hw_range_overlaps(ea, size, info)) {
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if (dawrx_constraints) {
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info->type |= HW_BRK_TYPE_EXTRANEOUS_IRQ;
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return true;
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}
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}
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return false;
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}
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static int cache_op_size(void)
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{
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#ifdef __powerpc64__
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return ppc64_caches.l1d.block_size;
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#else
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return L1_CACHE_BYTES;
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#endif
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}
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void wp_get_instr_detail(struct pt_regs *regs, struct ppc_inst *instr,
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int *type, int *size, unsigned long *ea)
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{
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struct instruction_op op;
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if (__get_user_instr_inatomic(*instr, (void __user *)regs->nip))
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return;
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analyse_instr(&op, regs, *instr);
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*type = GETTYPE(op.type);
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*ea = op.ea;
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#ifdef __powerpc64__
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if (!(regs->msr & MSR_64BIT))
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*ea &= 0xffffffffUL;
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#endif
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*size = GETSIZE(op.type);
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if (*type == CACHEOP) {
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*size = cache_op_size();
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*ea &= ~(*size - 1);
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} else if (*type == LOAD_VMX || *type == STORE_VMX) {
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*ea &= ~(*size - 1);
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}
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}
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