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mmc: sdhci-msm: Implement set_clock callback for sdhci-msm
sdhci-msm controller may have different clk-rates for each bus speed mode. Thus implement set_clock callback for sdhci-msm driver. Signed-off-by: Sahitya Tummala <stummala@codeaurora.org> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -84,6 +84,7 @@ struct sdhci_msm_host {
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struct clk *pclk; /* SDHC peripheral bus clock */
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struct clk *bus_clk; /* SDHC bus voter clock */
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struct clk *xo_clk; /* TCXO clk needed for FLL feature of cm_dll*/
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unsigned long clk_rate;
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struct mmc_host *mmc;
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bool use_14lpp_dll_reset;
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};
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@ -571,6 +572,69 @@ static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
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return SDHCI_MSM_MIN_CLOCK;
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}
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/**
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* __sdhci_msm_set_clock - sdhci_msm clock control.
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*
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* Description:
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* MSM controller does not use internal divider and
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* instead directly control the GCC clock as per
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* HW recommendation.
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**/
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void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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u16 clk;
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/*
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* Keep actual_clock as zero -
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* - since there is no divider used so no need of having actual_clock.
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* - MSM controller uses SDCLK for data timeout calculation. If
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* actual_clock is zero, host->clock is taken for calculation.
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*/
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host->mmc->actual_clock = 0;
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sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
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if (clock == 0)
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return;
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/*
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* MSM controller do not use clock divider.
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* Thus read SDHCI_CLOCK_CONTROL and only enable
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* clock with no divider value programmed.
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*/
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clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
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sdhci_enable_clk(host, clk);
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}
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/* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
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static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
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int rc;
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if (!clock) {
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msm_host->clk_rate = clock;
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goto out;
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}
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spin_unlock_irq(&host->lock);
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rc = clk_set_rate(msm_host->clk, clock);
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if (rc) {
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pr_err("%s: Failed to set clock at rate %u\n",
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mmc_hostname(host->mmc), clock);
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goto out_lock;
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}
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msm_host->clk_rate = clock;
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pr_debug("%s: Setting clock at rate %lu\n",
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mmc_hostname(host->mmc), clk_get_rate(msm_host->clk));
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out_lock:
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spin_lock_irq(&host->lock);
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out:
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__sdhci_msm_set_clock(host, clock);
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}
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static const struct of_device_id sdhci_msm_dt_match[] = {
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{ .compatible = "qcom,sdhci-msm-v4" },
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{},
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@ -581,7 +645,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
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static const struct sdhci_ops sdhci_msm_ops = {
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.platform_execute_tuning = sdhci_msm_execute_tuning,
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.reset = sdhci_reset,
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.set_clock = sdhci_set_clock,
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.set_clock = sdhci_msm_set_clock,
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.get_min_clock = sdhci_msm_get_min_clock,
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.get_max_clock = sdhci_msm_get_max_clock,
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.set_bus_width = sdhci_set_bus_width,
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