mirror of
https://github.com/edk2-porting/linux-next.git
synced 2024-12-25 13:43:55 +08:00
Merge branch 'topic/dirn_remove' into for-linus
This commit is contained in:
commit
edc329fbb8
@ -1320,7 +1320,7 @@ atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
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if (unlikely(!is_slave_direction(direction)))
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goto err_out;
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if (sconfig->direction == DMA_MEM_TO_DEV)
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if (direction == DMA_MEM_TO_DEV)
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reg_width = convert_buswidth(sconfig->dst_addr_width);
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else
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reg_width = convert_buswidth(sconfig->src_addr_width);
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|
@ -778,14 +778,6 @@ static int bcm2835_dma_slave_config(struct dma_chan *chan,
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{
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struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
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if ((cfg->direction == DMA_DEV_TO_MEM &&
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cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
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(cfg->direction == DMA_MEM_TO_DEV &&
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cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
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!is_slave_direction(cfg->direction)) {
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return -EINVAL;
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}
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c->cfg = *cfg;
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return 0;
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|
@ -1306,6 +1306,7 @@ struct coh901318_chan {
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unsigned long nbr_active_done;
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unsigned long busy;
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struct dma_slave_config config;
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u32 addr;
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u32 ctrl;
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@ -1402,6 +1403,10 @@ static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
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return container_of(chan, struct coh901318_chan, chan);
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}
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static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
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struct dma_slave_config *config,
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enum dma_transfer_direction direction);
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static inline const struct coh901318_params *
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cohc_chan_param(struct coh901318_chan *cohc)
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{
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@ -2360,6 +2365,8 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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if (lli == NULL)
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goto err_dma_alloc;
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coh901318_dma_set_runtimeconfig(chan, &cohc->config, direction);
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/* initiate allocated lli list */
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ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
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cohc->addr,
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@ -2499,7 +2506,8 @@ static const struct burst_table burst_sizes[] = {
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};
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static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
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struct dma_slave_config *config)
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struct dma_slave_config *config,
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enum dma_transfer_direction direction)
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{
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struct coh901318_chan *cohc = to_coh901318_chan(chan);
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dma_addr_t addr;
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@ -2509,11 +2517,11 @@ static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
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int i = 0;
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/* We only support mem to per or per to mem transfers */
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if (config->direction == DMA_DEV_TO_MEM) {
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if (direction == DMA_DEV_TO_MEM) {
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addr = config->src_addr;
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addr_width = config->src_addr_width;
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maxburst = config->src_maxburst;
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} else if (config->direction == DMA_MEM_TO_DEV) {
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} else if (direction == DMA_MEM_TO_DEV) {
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addr = config->dst_addr;
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addr_width = config->dst_addr_width;
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maxburst = config->dst_maxburst;
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@ -2579,6 +2587,16 @@ static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
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return 0;
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}
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static int coh901318_dma_slave_config(struct dma_chan *chan,
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struct dma_slave_config *config)
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{
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struct coh901318_chan *cohc = to_coh901318_chan(chan);
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memcpy(&cohc->config, config, sizeof(*config));
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return 0;
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}
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static void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
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struct coh901318_base *base)
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{
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@ -2684,7 +2702,7 @@ static int __init coh901318_probe(struct platform_device *pdev)
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base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
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base->dma_slave.device_tx_status = coh901318_tx_status;
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base->dma_slave.device_issue_pending = coh901318_issue_pending;
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base->dma_slave.device_config = coh901318_dma_set_runtimeconfig;
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base->dma_slave.device_config = coh901318_dma_slave_config;
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base->dma_slave.device_pause = coh901318_pause;
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base->dma_slave.device_resume = coh901318_resume;
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base->dma_slave.device_terminate_all = coh901318_terminate_all;
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@ -2707,7 +2725,7 @@ static int __init coh901318_probe(struct platform_device *pdev)
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base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
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base->dma_memcpy.device_tx_status = coh901318_tx_status;
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base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
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base->dma_memcpy.device_config = coh901318_dma_set_runtimeconfig;
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base->dma_memcpy.device_config = coh901318_dma_slave_config;
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base->dma_memcpy.device_pause = coh901318_pause;
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base->dma_memcpy.device_resume = coh901318_resume;
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base->dma_memcpy.device_terminate_all = coh901318_terminate_all;
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|
@ -113,6 +113,7 @@ struct jz4740_dma_desc {
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struct jz4740_dmaengine_chan {
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struct virt_dma_chan vchan;
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unsigned int id;
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struct dma_slave_config config;
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dma_addr_t fifo_addr;
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unsigned int transfer_shift;
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@ -203,8 +204,9 @@ static enum jz4740_dma_transfer_size jz4740_dma_maxburst(u32 maxburst)
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return JZ4740_DMA_TRANSFER_SIZE_32BYTE;
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}
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static int jz4740_dma_slave_config(struct dma_chan *c,
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struct dma_slave_config *config)
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static int jz4740_dma_slave_config_write(struct dma_chan *c,
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struct dma_slave_config *config,
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enum dma_transfer_direction direction)
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{
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struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
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struct jz4740_dma_dev *dmadev = jz4740_dma_chan_get_dev(chan);
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@ -214,7 +216,7 @@ static int jz4740_dma_slave_config(struct dma_chan *c,
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enum jz4740_dma_flags flags;
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uint32_t cmd;
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switch (config->direction) {
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switch (direction) {
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case DMA_MEM_TO_DEV:
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flags = JZ4740_DMA_SRC_AUTOINC;
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transfer_size = jz4740_dma_maxburst(config->dst_maxburst);
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@ -265,6 +267,15 @@ static int jz4740_dma_slave_config(struct dma_chan *c,
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return 0;
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}
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static int jz4740_dma_slave_config(struct dma_chan *c,
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struct dma_slave_config *config)
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{
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struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
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memcpy(&chan->config, config, sizeof(*config));
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return 0;
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}
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static int jz4740_dma_terminate_all(struct dma_chan *c)
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{
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struct jz4740_dmaengine_chan *chan = to_jz4740_dma_chan(c);
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@ -407,6 +418,8 @@ static struct dma_async_tx_descriptor *jz4740_dma_prep_slave_sg(
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desc->direction = direction;
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desc->cyclic = false;
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jz4740_dma_slave_config_write(c, &chan->config, direction);
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return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
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}
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@ -438,6 +451,8 @@ static struct dma_async_tx_descriptor *jz4740_dma_prep_dma_cyclic(
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desc->direction = direction;
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desc->cyclic = true;
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jz4740_dma_slave_config_write(c, &chan->config, direction);
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return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
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}
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@ -886,12 +886,7 @@ static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
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*/
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u32 s = dw->pdata->is_idma32 ? 1 : 2;
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/* Check if chan will be configured for slave transfers */
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if (!is_slave_direction(sconfig->direction))
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return -EINVAL;
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memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
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dwc->direction = sconfig->direction;
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sc->src_maxburst = sc->src_maxburst > 1 ? fls(sc->src_maxburst) - s : 0;
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sc->dst_maxburst = sc->dst_maxburst > 1 ? fls(sc->dst_maxburst) - s : 0;
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|
@ -109,6 +109,9 @@
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#define DMA_MAX_CHAN_DESCRIPTORS 32
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struct ep93xx_dma_engine;
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static int ep93xx_dma_slave_config_write(struct dma_chan *chan,
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enum dma_transfer_direction dir,
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struct dma_slave_config *config);
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/**
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* struct ep93xx_dma_desc - EP93xx specific transaction descriptor
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@ -180,6 +183,7 @@ struct ep93xx_dma_chan {
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struct list_head free_list;
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u32 runtime_addr;
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u32 runtime_ctrl;
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struct dma_slave_config slave_config;
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};
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/**
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@ -1051,6 +1055,8 @@ ep93xx_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
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return NULL;
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}
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ep93xx_dma_slave_config_write(chan, dir, &edmac->slave_config);
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first = NULL;
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for_each_sg(sgl, sg, sg_len, i) {
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size_t len = sg_dma_len(sg);
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@ -1136,6 +1142,8 @@ ep93xx_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
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return NULL;
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}
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ep93xx_dma_slave_config_write(chan, dir, &edmac->slave_config);
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/* Split the buffer into period size chunks */
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first = NULL;
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for (offset = 0; offset < buf_len; offset += period_len) {
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@ -1227,6 +1235,17 @@ static int ep93xx_dma_slave_config(struct dma_chan *chan,
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struct dma_slave_config *config)
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{
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struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
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|
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memcpy(&edmac->slave_config, config, sizeof(*config));
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return 0;
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}
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static int ep93xx_dma_slave_config_write(struct dma_chan *chan,
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enum dma_transfer_direction dir,
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struct dma_slave_config *config)
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{
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struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
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enum dma_slave_buswidth width;
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unsigned long flags;
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u32 addr, ctrl;
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@ -1234,7 +1253,7 @@ static int ep93xx_dma_slave_config(struct dma_chan *chan,
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if (!edmac->edma->m2m)
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return -EINVAL;
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|
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switch (config->direction) {
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switch (dir) {
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case DMA_DEV_TO_MEM:
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width = config->src_addr_width;
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addr = config->src_addr;
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|
@ -348,10 +348,6 @@ static int hsu_dma_slave_config(struct dma_chan *chan,
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{
|
||||
struct hsu_dma_chan *hsuc = to_hsu_dma_chan(chan);
|
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|
||||
/* Check if chan will be configured for slave transfers */
|
||||
if (!is_slave_direction(config->direction))
|
||||
return -EINVAL;
|
||||
|
||||
memcpy(&hsuc->config, config, sizeof(hsuc->config));
|
||||
|
||||
return 0;
|
||||
|
@ -408,10 +408,6 @@ static int idma64_slave_config(struct dma_chan *chan,
|
||||
{
|
||||
struct idma64_chan *idma64c = to_idma64_chan(chan);
|
||||
|
||||
/* Check if chan will be configured for slave transfers */
|
||||
if (!is_slave_direction(config->direction))
|
||||
return -EINVAL;
|
||||
|
||||
memcpy(&idma64c->config, config, sizeof(idma64c->config));
|
||||
|
||||
convert_burst(&idma64c->config.src_maxburst);
|
||||
|
@ -162,6 +162,7 @@ struct imxdma_channel {
|
||||
bool enabled_2d;
|
||||
int slot_2d;
|
||||
unsigned int irq;
|
||||
struct dma_slave_config config;
|
||||
};
|
||||
|
||||
enum imx_dma_type {
|
||||
@ -675,14 +676,15 @@ static int imxdma_terminate_all(struct dma_chan *chan)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int imxdma_config(struct dma_chan *chan,
|
||||
struct dma_slave_config *dmaengine_cfg)
|
||||
static int imxdma_config_write(struct dma_chan *chan,
|
||||
struct dma_slave_config *dmaengine_cfg,
|
||||
enum dma_transfer_direction direction)
|
||||
{
|
||||
struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
|
||||
struct imxdma_engine *imxdma = imxdmac->imxdma;
|
||||
unsigned int mode = 0;
|
||||
|
||||
if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
|
||||
if (direction == DMA_DEV_TO_MEM) {
|
||||
imxdmac->per_address = dmaengine_cfg->src_addr;
|
||||
imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
|
||||
imxdmac->word_size = dmaengine_cfg->src_addr_width;
|
||||
@ -723,6 +725,16 @@ static int imxdma_config(struct dma_chan *chan,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int imxdma_config(struct dma_chan *chan,
|
||||
struct dma_slave_config *dmaengine_cfg)
|
||||
{
|
||||
struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
|
||||
|
||||
memcpy(&imxdmac->config, dmaengine_cfg, sizeof(*dmaengine_cfg));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static enum dma_status imxdma_tx_status(struct dma_chan *chan,
|
||||
dma_cookie_t cookie,
|
||||
struct dma_tx_state *txstate)
|
||||
@ -905,6 +917,8 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
|
||||
desc->desc.callback = NULL;
|
||||
desc->desc.callback_param = NULL;
|
||||
|
||||
imxdma_config_write(chan, &imxdmac->config, direction);
|
||||
|
||||
return &desc->desc;
|
||||
}
|
||||
|
||||
|
@ -87,10 +87,10 @@ struct k3_dma_chan {
|
||||
struct virt_dma_chan vc;
|
||||
struct k3_dma_phy *phy;
|
||||
struct list_head node;
|
||||
enum dma_transfer_direction dir;
|
||||
dma_addr_t dev_addr;
|
||||
enum dma_status status;
|
||||
bool cyclic;
|
||||
struct dma_slave_config slave_config;
|
||||
};
|
||||
|
||||
struct k3_dma_phy {
|
||||
@ -118,6 +118,10 @@ struct k3_dma_dev {
|
||||
|
||||
#define to_k3_dma(dmadev) container_of(dmadev, struct k3_dma_dev, slave)
|
||||
|
||||
static int k3_dma_config_write(struct dma_chan *chan,
|
||||
enum dma_transfer_direction dir,
|
||||
struct dma_slave_config *cfg);
|
||||
|
||||
static struct k3_dma_chan *to_k3_chan(struct dma_chan *chan)
|
||||
{
|
||||
return container_of(chan, struct k3_dma_chan, vc.chan);
|
||||
@ -501,14 +505,8 @@ static struct dma_async_tx_descriptor *k3_dma_prep_memcpy(
|
||||
copy = min_t(size_t, len, DMA_MAX_SIZE);
|
||||
k3_dma_fill_desc(ds, dst, src, copy, num++, c->ccfg);
|
||||
|
||||
if (c->dir == DMA_MEM_TO_DEV) {
|
||||
src += copy;
|
||||
} else if (c->dir == DMA_DEV_TO_MEM) {
|
||||
dst += copy;
|
||||
} else {
|
||||
src += copy;
|
||||
dst += copy;
|
||||
}
|
||||
src += copy;
|
||||
dst += copy;
|
||||
len -= copy;
|
||||
} while (len);
|
||||
|
||||
@ -542,6 +540,7 @@ static struct dma_async_tx_descriptor *k3_dma_prep_slave_sg(
|
||||
if (!ds)
|
||||
return NULL;
|
||||
num = 0;
|
||||
k3_dma_config_write(chan, dir, &c->slave_config);
|
||||
|
||||
for_each_sg(sgl, sg, sglen, i) {
|
||||
addr = sg_dma_address(sg);
|
||||
@ -602,6 +601,7 @@ k3_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
|
||||
avail = buf_len;
|
||||
total = avail;
|
||||
num = 0;
|
||||
k3_dma_config_write(chan, dir, &c->slave_config);
|
||||
|
||||
if (period_len < modulo)
|
||||
modulo = period_len;
|
||||
@ -642,18 +642,26 @@ static int k3_dma_config(struct dma_chan *chan,
|
||||
struct dma_slave_config *cfg)
|
||||
{
|
||||
struct k3_dma_chan *c = to_k3_chan(chan);
|
||||
|
||||
memcpy(&c->slave_config, cfg, sizeof(*cfg));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int k3_dma_config_write(struct dma_chan *chan,
|
||||
enum dma_transfer_direction dir,
|
||||
struct dma_slave_config *cfg)
|
||||
{
|
||||
struct k3_dma_chan *c = to_k3_chan(chan);
|
||||
u32 maxburst = 0, val = 0;
|
||||
enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
|
||||
|
||||
if (cfg == NULL)
|
||||
return -EINVAL;
|
||||
c->dir = cfg->direction;
|
||||
if (c->dir == DMA_DEV_TO_MEM) {
|
||||
if (dir == DMA_DEV_TO_MEM) {
|
||||
c->ccfg = CX_CFG_DSTINCR;
|
||||
c->dev_addr = cfg->src_addr;
|
||||
maxburst = cfg->src_maxburst;
|
||||
width = cfg->src_addr_width;
|
||||
} else if (c->dir == DMA_MEM_TO_DEV) {
|
||||
} else if (dir == DMA_MEM_TO_DEV) {
|
||||
c->ccfg = CX_CFG_SRCINCR;
|
||||
c->dev_addr = cfg->dst_addr;
|
||||
maxburst = cfg->dst_maxburst;
|
||||
|
@ -116,6 +116,7 @@ struct mmp_tdma_chan {
|
||||
u32 burst_sz;
|
||||
enum dma_slave_buswidth buswidth;
|
||||
enum dma_status status;
|
||||
struct dma_slave_config slave_config;
|
||||
|
||||
int idx;
|
||||
enum mmp_tdma_type type;
|
||||
@ -139,6 +140,10 @@ struct mmp_tdma_device {
|
||||
|
||||
#define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan)
|
||||
|
||||
static int mmp_tdma_config_write(struct dma_chan *chan,
|
||||
enum dma_transfer_direction dir,
|
||||
struct dma_slave_config *dmaengine_cfg);
|
||||
|
||||
static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys)
|
||||
{
|
||||
writel(phys, tdmac->reg_base + TDNDPR);
|
||||
@ -442,6 +447,8 @@ static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic(
|
||||
if (!desc)
|
||||
goto err_out;
|
||||
|
||||
mmp_tdma_config_write(chan, direction, &tdmac->slave_config);
|
||||
|
||||
while (buf < buf_len) {
|
||||
desc = &tdmac->desc_arr[i];
|
||||
|
||||
@ -495,7 +502,18 @@ static int mmp_tdma_config(struct dma_chan *chan,
|
||||
{
|
||||
struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
|
||||
|
||||
if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
|
||||
memcpy(&tdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mmp_tdma_config_write(struct dma_chan *chan,
|
||||
enum dma_transfer_direction dir,
|
||||
struct dma_slave_config *dmaengine_cfg)
|
||||
{
|
||||
struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
|
||||
|
||||
if (dir == DMA_DEV_TO_MEM) {
|
||||
tdmac->dev_addr = dmaengine_cfg->src_addr;
|
||||
tdmac->burst_sz = dmaengine_cfg->src_maxburst;
|
||||
tdmac->buswidth = dmaengine_cfg->src_addr_width;
|
||||
@ -504,7 +522,7 @@ static int mmp_tdma_config(struct dma_chan *chan,
|
||||
tdmac->burst_sz = dmaengine_cfg->dst_maxburst;
|
||||
tdmac->buswidth = dmaengine_cfg->dst_addr_width;
|
||||
}
|
||||
tdmac->dir = dmaengine_cfg->direction;
|
||||
tdmac->dir = dir;
|
||||
|
||||
return mmp_tdma_config_chan(chan);
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user