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SoC updates for omaps for v4.19 merge window

Browse Source 
These changes are mostly PM related changes for am335x and
 am437x to support RTC only suspend mode. Some of the clock
 and driver related chances are still pending so it's not
 yet fully functional.
 
 Also included is a change for PM debug sysfs entry to use
 DEFINE_SHOW_ATTRIBUTE.
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Merge tag 'omap-for-v4.19/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc

SoC updates for omaps for v4.19 merge window

These changes are mostly PM related changes for am335x and
am437x to support RTC only suspend mode. Some of the clock
and driver related chances are still pending so it's not
yet fully functional.

Also included is a change for PM debug sysfs entry to use
DEFINE_SHOW_ATTRIBUTE.

* tag 'omap-for-v4.19/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: sleep33/43xx: Add RTC-Mode support
  ARM: OMAP2+: sleep33/43xx: Make sleep actions configurable
  ARM: OMAP2+: reuse DEFINE_SHOW_ATTRIBUTE() macro
  ARM: hwmod: RTC: Don't assume lock/unlock will be called with irq enabled

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2018-07-14 14:45:14 -07:00
commit edc07c0012
8 changed files with 229 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm/mach-omap2/omap_hwmod_reset.c
View File

@ -92,11 +92,13 @@ static void omap_rtc_wait_not_busy(struct omap_hwmod *oh)
*/
void omap_hwmod_rtc_unlock(struct omap_hwmod *oh)
{
local_irq_disable();
unsigned long flags;
local_irq_save(flags);
omap_rtc_wait_not_busy(oh);
omap_hwmod_write(OMAP_RTC_KICK0_VALUE, oh, OMAP_RTC_KICK0_REG);
omap_hwmod_write(OMAP_RTC_KICK1_VALUE, oh, OMAP_RTC_KICK1_REG);
local_irq_enable();
local_irq_restore(flags);
}
/**
@ -110,9 +112,11 @@ void omap_hwmod_rtc_unlock(struct omap_hwmod *oh)
*/
void omap_hwmod_rtc_lock(struct omap_hwmod *oh)
{
local_irq_disable();
unsigned long flags;
local_irq_save(flags);
omap_rtc_wait_not_busy(oh);
omap_hwmod_write(0x0, oh, OMAP_RTC_KICK0_REG);
omap_hwmod_write(0x0, oh, OMAP_RTC_KICK1_REG);
local_irq_enable();
local_irq_restore(flags);
}

2
arch/arm/mach-omap2/pm-asm-offsets.c
View File

@ -27,6 +27,8 @@ int main(void)
offsetof(struct am33xx_pm_ro_sram_data, amx3_pm_sram_data_virt));
DEFINE(AMX3_PM_RO_SRAM_DATA_PHYS_OFFSET,
offsetof(struct am33xx_pm_ro_sram_data, amx3_pm_sram_data_phys));
DEFINE(AMX3_PM_RTC_BASE_VIRT_OFFSET,
offsetof(struct am33xx_pm_ro_sram_data, rtc_base_virt));
DEFINE(AMX3_PM_RO_SRAM_DATA_SIZE,
sizeof(struct am33xx_pm_ro_sram_data));

37
arch/arm/mach-omap2/pm-debug.c
View File

@ -47,11 +47,6 @@ static int pm_dbg_init_done;
static int pm_dbg_init(void);
enum {
DEBUG_FILE_COUNTERS = 0,
DEBUG_FILE_TIMERS,
};
static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = {
"OFF",
"RET",
@ -141,39 +136,21 @@ static int pwrdm_dbg_show_timer(struct powerdomain *pwrdm, void *user)
return 0;
}
static int pm_dbg_show_counters(struct seq_file *s, void *unused)
static int pm_dbg_counters_show(struct seq_file *s, void *unused)
{
pwrdm_for_each(pwrdm_dbg_show_counter, s);
clkdm_for_each(clkdm_dbg_show_counter, s);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(pm_dbg_counters);
static int pm_dbg_show_timers(struct seq_file *s, void *unused)
static int pm_dbg_timers_show(struct seq_file *s, void *unused)
{
pwrdm_for_each(pwrdm_dbg_show_timer, s);
return 0;
}
static int pm_dbg_open(struct inode *inode, struct file *file)
{
switch ((int)inode->i_private) {
case DEBUG_FILE_COUNTERS:
return single_open(file, pm_dbg_show_counters,
&inode->i_private);
case DEBUG_FILE_TIMERS:
default:
return single_open(file, pm_dbg_show_timers,
&inode->i_private);
}
}
static const struct file_operations debug_fops = {
.open = pm_dbg_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
DEFINE_SHOW_ATTRIBUTE(pm_dbg_timers);
static int pwrdm_suspend_get(void *data, u64 *val)
{
@ -259,10 +236,8 @@ static int __init pm_dbg_init(void)
if (!d)
return -EINVAL;
(void) debugfs_create_file("count", S_IRUGO,
d, (void *)DEBUG_FILE_COUNTERS, &debug_fops);
(void) debugfs_create_file("time", S_IRUGO,
d, (void *)DEBUG_FILE_TIMERS, &debug_fops);
(void) debugfs_create_file("count", 0444, d, NULL, &pm_dbg_counters_fops);
(void) debugfs_create_file("time", 0444, d, NULL, &pm_dbg_timers_fops);
pwrdm_for_each(pwrdms_setup, (void *)d);

20
arch/arm/mach-omap2/pm33xx-core.c
View File

@ -26,6 +26,7 @@
static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm;
static struct clockdomain *gfx_l4ls_clkdm;
static void __iomem *scu_base;
static struct omap_hwmod *rtc_oh;
static int __init am43xx_map_scu(void)
{
@ -106,12 +107,13 @@ static void amx3_post_suspend_common(void)
pr_err("PM: GFX domain did not transition: %x\n", status);
}
static int am33xx_suspend(unsigned int state, int (*fn)(unsigned long))
static int am33xx_suspend(unsigned int state, int (*fn)(unsigned long),
unsigned long args)
{
int ret = 0;
amx3_pre_suspend_common();
ret = cpu_suspend(0, fn);
ret = cpu_suspend(args, fn);
amx3_post_suspend_common();
/*
@ -128,13 +130,14 @@ static int am33xx_suspend(unsigned int state, int (*fn)(unsigned long))
return ret;
}
static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long))
static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long),
unsigned long args)
{
int ret = 0;
amx3_pre_suspend_common();
scu_power_mode(scu_base, SCU_PM_POWEROFF);
ret = cpu_suspend(0, fn);
ret = cpu_suspend(args, fn);
scu_power_mode(scu_base, SCU_PM_NORMAL);
amx3_post_suspend_common();
@ -151,16 +154,25 @@ static struct am33xx_pm_sram_addr *amx3_get_sram_addrs(void)
return NULL;
}
void __iomem *am43xx_get_rtc_base_addr(void)
{
rtc_oh = omap_hwmod_lookup("rtc");
return omap_hwmod_get_mpu_rt_va(rtc_oh);
}
static struct am33xx_pm_platform_data am33xx_ops = {
.init = am33xx_suspend_init,
.soc_suspend = am33xx_suspend,
.get_sram_addrs = amx3_get_sram_addrs,
.get_rtc_base_addr = am43xx_get_rtc_base_addr,
};
static struct am33xx_pm_platform_data am43xx_ops = {
.init = am43xx_suspend_init,
.soc_suspend = am43xx_suspend,
.get_sram_addrs = amx3_get_sram_addrs,
.get_rtc_base_addr = am43xx_get_rtc_base_addr,
};
static struct am33xx_pm_platform_data *am33xx_pm_get_pdata(void)

52
arch/arm/mach-omap2/sleep33xx.S
View File

@ -8,6 +8,7 @@
#include <generated/ti-pm-asm-offsets.h>
#include <linux/linkage.h>
#include <linux/platform_data/pm33xx.h>
#include <linux/ti-emif-sram.h>
#include <asm/assembler.h>
#include <asm/memory.h>
@ -19,12 +20,25 @@
#define AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE 0x0003
#define AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE 0x0002
/* replicated define because linux/bitops.h cannot be included in assembly */
#define BIT(nr) (1 << (nr))
.arm
.align 3
ENTRY(am33xx_do_wfi)
stmfd sp!, {r4 - r11, lr} @ save registers on stack
/* Save wfi_flags arg to data space */
mov r4, r0
adr r3, am33xx_pm_ro_sram_data
ldr r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET]
str r4, [r2, #AMX3_PM_WFI_FLAGS_OFFSET]
/* Only flush cache is we know we are losing MPU context */
tst r4, #WFI_FLAG_FLUSH_CACHE
beq cache_skip_flush
/*
* Flush all data from the L1 and L2 data cache before disabling
* SCTLR.C bit.
@ -48,14 +62,33 @@ ENTRY(am33xx_do_wfi)
ldr r1, kernel_flush
blx r1
adr r3, am33xx_pm_ro_sram_data
ldr r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET]
ldr r4, [r2, #AMX3_PM_WFI_FLAGS_OFFSET]
cache_skip_flush:
/* Check if we want self refresh */
tst r4, #WFI_FLAG_SELF_REFRESH
beq emif_skip_enter_sr
adr r9, am33xx_emif_sram_table
ldr r3, [r9, #EMIF_PM_ENTER_SR_OFFSET]
blx r3
emif_skip_enter_sr:
/* Only necessary if PER is losing context */
tst r4, #WFI_FLAG_SAVE_EMIF
beq emif_skip_save
ldr r3, [r9, #EMIF_PM_SAVE_CONTEXT_OFFSET]
blx r3
emif_skip_save:
/* Only can disable EMIF if we have entered self refresh */
tst r4, #WFI_FLAG_SELF_REFRESH
beq emif_skip_disable
/* Disable EMIF */
ldr r1, virt_emif_clkctrl
ldr r2, [r1]
@ -69,6 +102,10 @@ wait_emif_disable:
cmp r2, r3
bne wait_emif_disable
emif_skip_disable:
tst r4, #WFI_FLAG_WAKE_M3
beq wkup_m3_skip
/*
* For the MPU WFI to be registered as an interrupt
* to WKUP_M3, MPU_CLKCTRL.MODULEMODE needs to be set
@ -79,6 +116,7 @@ wait_emif_disable:
bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE
str r2, [r1]
wkup_m3_skip:
/*
* Execute an ISB instruction to ensure that all of the
* CP15 register changes have been committed.
@ -132,10 +170,18 @@ wait_emif_enable:
cmp r2, r3
bne wait_emif_enable
/* Only necessary if PER is losing context */
tst r4, #WFI_FLAG_SELF_REFRESH
beq emif_skip_exit_sr_abt
adr r9, am33xx_emif_sram_table
ldr r1, [r9, #EMIF_PM_ABORT_SR_OFFSET]
blx r1
emif_skip_exit_sr_abt:
tst r4, #WFI_FLAG_FLUSH_CACHE
beq cache_skip_restore
/*
* Set SCTLR.C bit to allow data cache allocation
*/
@ -144,6 +190,7 @@ wait_emif_enable:
mcr p15, 0, r0, c1, c0, 0
isb
cache_skip_restore:
/* Let the suspend code know about the abort */
mov r0, #1
ldmfd sp!, {r4 - r11, pc} @ restore regs and return
@ -181,8 +228,6 @@ ENDPROC(am33xx_resume_from_deep_sleep)
* Local variables
*/
.align
resume_addr:
.word cpu_resume - PAGE_OFFSET + 0x80000000
kernel_flush:
.word v7_flush_dcache_all
virt_mpu_clkctrl:
@ -205,6 +250,9 @@ ENTRY(am33xx_pm_sram)
.word am33xx_emif_sram_table
.word am33xx_pm_ro_sram_data
resume_addr:
.word cpu_resume - PAGE_OFFSET + 0x80000000
.align 3
ENTRY(am33xx_pm_ro_sram_data)
.space AMX3_PM_RO_SRAM_DATA_SIZE

110
arch/arm/mach-omap2/sleep43xx.S
View File

@ -9,7 +9,7 @@
#include <generated/ti-pm-asm-offsets.h>
#include <linux/linkage.h>
#include <linux/ti-emif-sram.h>
#include <linux/platform_data/pm33xx.h>
#include <asm/assembler.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/memory.h>
@ -22,6 +22,9 @@
#include "prm33xx.h"
#include "prcm43xx.h"
/* replicated define because linux/bitops.h cannot be included in assembly */
#define BIT(nr) (1 << (nr))
#define AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED 0x00030000
#define AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE 0x0003
#define AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE 0x0002
@ -45,12 +48,25 @@
AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET)
#define AM43XX_PRM_EMIF_CTRL_OFFSET 0x0030
#define RTC_SECONDS_REG 0x0
#define RTC_PMIC_REG 0x98
#define RTC_PMIC_POWER_EN BIT(16)
#define RTC_PMIC_EXT_WAKEUP_STS BIT(12)
#define RTC_PMIC_EXT_WAKEUP_POL BIT(4)
#define RTC_PMIC_EXT_WAKEUP_EN BIT(0)
.arm
.align 3
ENTRY(am43xx_do_wfi)
stmfd sp!, {r4 - r11, lr} @ save registers on stack
/* Save wfi_flags arg to data space */
mov r4, r0
adr r3, am43xx_pm_ro_sram_data
ldr r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET]
str r4, [r2, #AMX3_PM_WFI_FLAGS_OFFSET]
#ifdef CONFIG_CACHE_L2X0
/* Retrieve l2 cache virt address BEFORE we shut off EMIF */
ldr r1, get_l2cache_base
@ -58,6 +74,10 @@ ENTRY(am43xx_do_wfi)
mov r8, r0
#endif
/* Only flush cache is we know we are losing MPU context */
tst r4, #WFI_FLAG_FLUSH_CACHE
beq cache_skip_flush
/*
* Flush all data from the L1 and L2 data cache before disabling
* SCTLR.C bit.
@ -128,13 +148,47 @@ sync:
bne sync
#endif
/* Restore wfi_flags */
adr r3, am43xx_pm_ro_sram_data
ldr r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET]
ldr r4, [r2, #AMX3_PM_WFI_FLAGS_OFFSET]
cache_skip_flush:
/*
* If we are trying to enter RTC+DDR mode we must perform
* a read from the rtc address space to ensure translation
* presence in the TLB to avoid page table walk after DDR
* is unavailable.
*/
tst r4, #WFI_FLAG_RTC_ONLY
beq skip_rtc_va_refresh
adr r3, am43xx_pm_ro_sram_data
ldr r1, [r3, #AMX3_PM_RTC_BASE_VIRT_OFFSET]
ldr r0, [r1]
skip_rtc_va_refresh:
/* Check if we want self refresh */
tst r4, #WFI_FLAG_SELF_REFRESH
beq emif_skip_enter_sr
adr r9, am43xx_emif_sram_table
ldr r3, [r9, #EMIF_PM_ENTER_SR_OFFSET]
blx r3
emif_skip_enter_sr:
/* Only necessary if PER is losing context */
tst r4, #WFI_FLAG_SAVE_EMIF
beq emif_skip_save
ldr r3, [r9, #EMIF_PM_SAVE_CONTEXT_OFFSET]
blx r3
blx r3
emif_skip_save:
/* Only can disable EMIF if we have entered self refresh */
tst r4, #WFI_FLAG_SELF_REFRESH
beq emif_skip_disable
/* Disable EMIF */
ldr r1, am43xx_virt_emif_clkctrl
@ -148,6 +202,38 @@ wait_emif_disable:
cmp r2, r3
bne wait_emif_disable
emif_skip_disable:
tst r4, #WFI_FLAG_RTC_ONLY
beq skip_rtc_only
adr r3, am43xx_pm_ro_sram_data
ldr r1, [r3, #AMX3_PM_RTC_BASE_VIRT_OFFSET]
ldr r0, [r1, #RTC_PMIC_REG]
orr r0, r0, #RTC_PMIC_POWER_EN
orr r0, r0, #RTC_PMIC_EXT_WAKEUP_STS
orr r0, r0, #RTC_PMIC_EXT_WAKEUP_EN
orr r0, r0, #RTC_PMIC_EXT_WAKEUP_POL
str r0, [r1, #RTC_PMIC_REG]
ldr r0, [r1, #RTC_PMIC_REG]
/* Wait for 2 seconds to lose power */
mov r3, #2
ldr r2, [r1, #RTC_SECONDS_REG]
rtc_loop:
ldr r0, [r1, #RTC_SECONDS_REG]
cmp r0, r2
beq rtc_loop
mov r2, r0
subs r3, r3, #1
bne rtc_loop
b re_enable_emif
skip_rtc_only:
tst r4, #WFI_FLAG_WAKE_M3
beq wkup_m3_skip
/*
* For the MPU WFI to be registered as an interrupt
* to WKUP_M3, MPU_CLKCTRL.MODULEMODE needs to be set
@ -165,6 +251,7 @@ wait_emif_disable:
mov r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_SW_SLEEP
str r2, [r1]
wkup_m3_skip:
/*
* Execute a barrier instruction to ensure that all cache,
* TLB and branch predictor maintenance operations issued
@ -209,6 +296,7 @@ wait_emif_disable:
mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
str r2, [r1]
re_enable_emif:
/* Re-enable EMIF */
ldr r1, am43xx_virt_emif_clkctrl
mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE
@ -218,6 +306,9 @@ wait_emif_enable:
cmp r2, r3
bne wait_emif_enable
tst r4, #WFI_FLAG_FLUSH_CACHE
beq cache_skip_restore
/*
* Set SCTLR.C bit to allow data cache allocation
*/
@ -226,9 +317,16 @@ wait_emif_enable:
mcr p15, 0, r0, c1, c0, 0
isb
ldr r1, [r9, #EMIF_PM_ABORT_SR_OFFSET]
blx r1
cache_skip_restore:
/* Only necessary if PER is losing context */
tst r4, #WFI_FLAG_SELF_REFRESH
beq emif_skip_exit_sr_abt
adr r9, am43xx_emif_sram_table
ldr r1, [r9, #EMIF_PM_ABORT_SR_OFFSET]
blx r1
emif_skip_exit_sr_abt:
/* Let the suspend code know about the abort */
mov r0, #1
ldmfd sp!, {r4 - r11, pc} @ restore regs and return
@ -333,8 +431,6 @@ ENDPROC(am43xx_resume_from_deep_sleep)
* Local variables
*/
.align
resume_addr:
.word cpu_resume - PAGE_OFFSET + 0x80000000
kernel_flush:
.word v7_flush_dcache_all
ddr_start:
@ -381,6 +477,8 @@ ENTRY(am43xx_pm_sram)
.word am43xx_emif_sram_table
.word am43xx_pm_ro_sram_data
resume_addr:
.word cpu_resume - PAGE_OFFSET + 0x80000000
.align 3
ENTRY(am43xx_pm_ro_sram_data)

16
drivers/soc/ti/pm33xx.c
View File

@ -41,6 +41,8 @@ static struct am33xx_pm_sram_addr *pm_sram;
static struct device *pm33xx_dev;
static struct wkup_m3_ipc *m3_ipc;
static unsigned long suspend_wfi_flags;
static u32 sram_suspend_address(unsigned long addr)
{
return ((unsigned long)am33xx_do_wfi_sram +
@ -53,7 +55,7 @@ static int am33xx_pm_suspend(suspend_state_t suspend_state)
int i, ret = 0;
ret = pm_ops->soc_suspend((unsigned long)suspend_state,
am33xx_do_wfi_sram);
am33xx_do_wfi_sram, suspend_wfi_flags);
if (ret) {
dev_err(pm33xx_dev, "PM: Kernel suspend failure\n");
@ -227,6 +229,7 @@ static int am33xx_push_sram_idle(void)
ro_sram_data.amx3_pm_sram_data_virt = ocmcram_location_data;
ro_sram_data.amx3_pm_sram_data_phys =
gen_pool_virt_to_phys(sram_pool_data, ocmcram_location_data);
ro_sram_data.rtc_base_virt = pm_ops->get_rtc_base_addr();
/* Save physical address to calculate resume offset during pm init */
am33xx_do_wfi_sram_phys = gen_pool_virt_to_phys(sram_pool,
@ -310,6 +313,17 @@ static int am33xx_pm_probe(struct platform_device *pdev)
suspend_set_ops(&am33xx_pm_ops);
#endif /* CONFIG_SUSPEND */
/*
* For a system suspend we must flush the caches, we want
* the DDR in self-refresh, we want to save the context
* of the EMIF, and we want the wkup_m3 to handle low-power
* transition.
*/
suspend_wfi_flags |= WFI_FLAG_FLUSH_CACHE;
suspend_wfi_flags |= WFI_FLAG_SELF_REFRESH;
suspend_wfi_flags |= WFI_FLAG_SAVE_EMIF;
suspend_wfi_flags |= WFI_FLAG_WAKE_M3;
ret = pm_ops->init();
if (ret) {
dev_err(dev, "Unable to call core pm init!\n");

29
include/linux/platform_data/pm33xx.h
View File

@ -12,6 +12,29 @@
#include <linux/kbuild.h>
#include <linux/types.h>
/*
* WFI Flags for sleep code control
*
* These flags allow PM code to exclude certain operations from happening
* in the low level ASM code found in sleep33xx.S and sleep43xx.S
*
* WFI_FLAG_FLUSH_CACHE: Flush the ARM caches and disable caching. Only
* needed when MPU will lose context.
* WFI_FLAG_SELF_REFRESH: Let EMIF place DDR memory into self-refresh and
* disable EMIF.
* WFI_FLAG_SAVE_EMIF: Save context of all EMIF registers and restore in
* resume path. Only needed if PER domain loses context
* and must also have WFI_FLAG_SELF_REFRESH set.
* WFI_FLAG_WAKE_M3: Disable MPU clock or clockdomain to cause wkup_m3 to
* execute when WFI instruction executes.
* WFI_FLAG_RTC_ONLY: Configure the RTC to enter RTC+DDR mode.
*/
#define WFI_FLAG_FLUSH_CACHE BIT(0)
#define WFI_FLAG_SELF_REFRESH BIT(1)
#define WFI_FLAG_SAVE_EMIF BIT(2)
#define WFI_FLAG_WAKE_M3 BIT(3)
#define WFI_FLAG_RTC_ONLY BIT(4)
#ifndef __ASSEMBLER__
struct am33xx_pm_sram_addr {
void (*do_wfi)(void);
@ -19,12 +42,15 @@ struct am33xx_pm_sram_addr {
unsigned long *resume_offset;
unsigned long *emif_sram_table;
unsigned long *ro_sram_data;
unsigned long resume_address;
};
struct am33xx_pm_platform_data {
int (*init)(void);
int (*soc_suspend)(unsigned int state, int (*fn)(unsigned long));
int (*soc_suspend)(unsigned int state, int (*fn)(unsigned long),
unsigned long args);
struct am33xx_pm_sram_addr *(*get_sram_addrs)(void);
void __iomem *(*get_rtc_base_addr)(void);
};
struct am33xx_pm_sram_data {
@ -36,6 +62,7 @@ struct am33xx_pm_sram_data {
struct am33xx_pm_ro_sram_data {
u32 amx3_pm_sram_data_virt;
u32 amx3_pm_sram_data_phys;
void __iomem *rtc_base_virt;
} __packed __aligned(8);
#endif /* __ASSEMBLER__ */