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pinctrl: atlas6: take mclk pin out of i2s pingroup
The I2S controller can output mclk to external audio codec. But by hardware design, some codecs need mclk and some codecs do not need mclk. So the mclk pin can be an independent pinctrl group, and the card driver can get it or not based on boards. Signed-off-by: Rongjun Ying <rongjun.ying@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -377,11 +377,25 @@ static const struct sirfsoc_padmux cko1_padmux = {
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static const unsigned cko1_pins[] = { 42 };
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static const struct sirfsoc_muxmask i2s_muxmask[] = {
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static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
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{
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.group = 1,
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.mask = BIT(10),
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}, {
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},
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};
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static const struct sirfsoc_padmux i2s_mclk_padmux = {
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.muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
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.muxmask = i2s_mclk_muxmask,
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.ctrlreg = SIRFSOC_RSC_PIN_MUX,
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.funcmask = BIT(3),
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.funcval = BIT(3),
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};
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static const unsigned i2s_mclk_pins[] = { 42 };
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static const struct sirfsoc_muxmask i2s_muxmask[] = {
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{
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.group = 3,
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.mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
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},
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@ -391,17 +405,12 @@ static const struct sirfsoc_padmux i2s_padmux = {
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.muxmask_counts = ARRAY_SIZE(i2s_muxmask),
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.muxmask = i2s_muxmask,
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.ctrlreg = SIRFSOC_RSC_PIN_MUX,
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.funcmask = BIT(3),
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.funcval = BIT(3),
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};
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static const unsigned i2s_pins[] = { 42, 98, 99, 100, 101 };
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static const unsigned i2s_pins[] = { 98, 99, 100, 101 };
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static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
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{
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.group = 1,
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.mask = BIT(10),
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}, {
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.group = 3,
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.mask = BIT(2) | BIT(3) | BIT(4),
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},
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@ -411,17 +420,12 @@ static const struct sirfsoc_padmux i2s_no_din_padmux = {
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.muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
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.muxmask = i2s_no_din_muxmask,
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.ctrlreg = SIRFSOC_RSC_PIN_MUX,
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.funcmask = BIT(3),
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.funcval = BIT(3),
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};
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static const unsigned i2s_no_din_pins[] = { 42, 98, 99, 100 };
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static const unsigned i2s_no_din_pins[] = { 98, 99, 100 };
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static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
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{
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.group = 1,
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.mask = BIT(10) | BIT(20) | BIT(23),
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}, {
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.group = 3,
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.mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
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},
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@ -431,11 +435,11 @@ static const struct sirfsoc_padmux i2s_6chn_padmux = {
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.muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
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.muxmask = i2s_6chn_muxmask,
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.ctrlreg = SIRFSOC_RSC_PIN_MUX,
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.funcmask = BIT(1) | BIT(3) | BIT(9),
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.funcval = BIT(1) | BIT(3) | BIT(9),
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.funcmask = BIT(1) | BIT(9),
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.funcval = BIT(1) | BIT(9),
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};
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static const unsigned i2s_6chn_pins[] = { 42, 52, 55, 98, 99, 100, 101 };
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static const unsigned i2s_6chn_pins[] = { 52, 55, 98, 99, 100, 101 };
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static const struct sirfsoc_muxmask ac97_muxmask[] = {
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{
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@ -977,6 +981,7 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
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SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
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SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
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SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
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SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
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SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
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SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
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SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
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@ -1029,6 +1034,7 @@ static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
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static const char * const
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uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
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static const char * const pulse_countgrp[] = { "pulse_countgrp" };
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static const char * const i2smclkgrp[] = { "i2smclkgrp" };
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static const char * const i2sgrp[] = { "i2sgrp" };
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static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
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static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
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@ -1089,6 +1095,7 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
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SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
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uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
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SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
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SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
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SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
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SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
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SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
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