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tty: serial: 8250: 8250_core: NXP SC16C2552 workaround
NXP SC16C2552 requires that we always write a reset to the RX FIFO and TX FIFO whenever we enable the FIFOs Cc: xe-kernel@external.cisco.com Signed-off-by: Steve Shih <sshih@cisco.com> Signed-off-by: David Singleton <davsingl@cisco.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -83,7 +83,8 @@ static const struct serial8250_config uart_config[] = {
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.name = "16550A",
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.fifo_size = 16,
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.tx_loadsz = 16,
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.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
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.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
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UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
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.rxtrig_bytes = {1, 4, 8, 14},
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.flags = UART_CAP_FIFO,
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},
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